Senior DFT Engineer

Senior DFT Engineer India

Work Location: Bangalore (Old Madras Road) Experience: 6 to 20 years Role Overview:

DFT engineer with strong experience in DFT design and

implementation Synthesis and Static Timing Analysis. In this role you will be responsible for DFT Synthesis and Timing analysis of several modules in digital ASICs

What youll be doing:

• Implement DFT methodologies and designs including JTAG Scan and Memory BIST at module and chip levels.
• Work closely with designers to enable designs to be DFTfriendly on modules and subsystems.

Help identify and fix design issues to enable smooth DFT implementation.

• Collaborate with physical implementation engineers and ASIC vendors in implementing DFT features for Automotive grade silicon.
• Collaborate with designers to run Synthesis on modules and subsystems and identify and fix RTL timing and implementation issues.
• Work closely with 3rd party IP vendors on proper DFT implementation for the IPs Define test structures debug structures and test plans.
• Create test vectors and simulate in various modes.
• Verify/Validate DFT requirements are being met in prePD and PostPD stages.
• Be a clear communicator with a proven ability to work across functions inside the company and with partners across the globe.

What youll have:

• Extensive experience in DFT techniques including JTAG Scan memory BIST scan compression ATPG vector generation Boundary Scan and DFT for mixedsignal and digital Ips.
• Must have worked with 3rd party mixedsignal IP vendors in implementing DFT.
• Experience with timing constraint generation for DFT modes.
• Experience with LBIST Initiation of test sequence on POST tests using IST controllers.
• Experience with IEEE JTAG 1149.1/1149.6/1500/1687 and BSDL ICL PDL.
• Experience with DFT verification and ATE test pattern generation.
• Experience with silicon bringup and debugging on ATE and insystem.
• BSEE MSEE 7 years experience or Ph.D. with 2 years of relevant experience in physical implementation of Digital ASICs.

Nice to haves:

• Familiarity with developing automotive grade silicon with AECQ100 qualification and ISO 26262