PLL CIRCUIT DESIGN ENGINEER

For over 15 years Trilyon has been at the forefront of providing comprehensive global workforce solutions and staffing services. Leveraging our extensive expertise across multiple domains such as Cloud technology Salesforce

AI Machine Learning and Technical Writing we consistently exceed expectations in catering to a wide range of requirements.

Currently we are seeking a PLL Circuit Design Engineer for one of our clients that is a leading multination corporation.

Role : PLL Circuit Design Engineer

Location: Folsom CA or Santa Clara CA or San Diego CA (Hybrid)

Type : Long Term Contract

Job Description:

• Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO chargepump dividers state machines LDO feedback and compensation techniques bandgap TDC interpolator circuits high speed buffers etc.
• Solid knowledge of industry standard tools and practices for analog circuit design
• Good knowledge in Physical design STA methodology scripts (Tcl) knowledge on Perl Python
• Qualityoriented mindset
• Strong and effective communication skills and team spirit
  
  

KEY RESPONSIBILITIES:

• Help design of building blocks of a PLL
• Run pretapeout verification flows to confirm design meets performance power reliability and timing requirements.

• Work closely with layout engineers to deliver the physical design as well as define production/benchlevel test plans with postsilicon characterization groups for silicon evaluation to ensure interlocked and highquality execution
  
  
  

PREFERRED EXPERIENCE:

• 35 years of professional experience in the semiconductor industry
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm
• Handson design experience in performance analog and hybrid Phase Locked Loops analogtodigital (ADC) digitaltoanalog (DAC) data converter VCO LDO bandgap charge pump opamps interpolator circuits.
• Experience with the following is a plus: Digital PLL techniques TDC or DSP and control theory experience related to digital PLLs Dual chargepump PLL designs FractionalN PLLs spreadspectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADEL and ADEXL and running MonteCarlo noise aging EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
• Have good experience with simulation tools such as Spectre Hspice AFS and MATLAB System Verilog Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre ICV or like)
• Proficiency in scripting languages like Perl Python matlab etc. is a plus.
• Able to work effectively in a team with good interpersonal skills enthusiasm and positive energy
• Possess strong analytical/problem solving skills and pronounced attention to details
• Must be a selfstarter and able to independently drive tasks to completion
  
  

ACADEMIC CREDENTIALS:

• Masters in electrical engineering or equivalent preferred