Memory Layout

• Designing custom layout standard cell and memory layout as well as memory leafcell layout library from scratch including top level integration.
• Demonstrating good knowledge of different types of memory architectures and optimized layout design for improved performance.
• Applying sound knowledge and handson experience in FinFET technology layout design and addressing design rule check (DRC) limitations.
• Proficiency in physical verification flow and debug processes such as DRC LVS ERC and boundary conditions.
• Expertise in using Cadence Virtuoso layout editor and Calibre physical verification flow.

• Relevant Bachelors or Masters degree in Electrical Engineering or a related field.
• Proven experience in custom layout standard cell and memory layout design.
• Demonstrated expertise in FinFET technology and layout design with a strong understanding of DRC limitations.
• Proficiency in utilizing Cadence Virtuoso layout editor and Calibre physical verification flow.

• Custom Layout
• Standard Cell
• Memory Layout Design
• FinFET Technology
• Physical Verification Flow

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