Fabric Architect

Fabric/Interconnect Architect

About The Job:

As fabric architect you will be responsible for the internal interconnect architecture specification and its performance power area requirements. This will cover both coherent and noncoherent interconnects and chiplettochiplet connections. You will be working with the Silicon team (eg. RTL/microarchitecture DV PD Perf DFT) members and industry consortiums such as UCIe.

Requirements:

• Thorough knowledge of large scale onchip fabric or onchip interconnect architecture
• Knowledge of onchip network protocols: AMBA AXI CHI ACE Tilelink or APB.
• Knowledge of cache coherent memory systems and interconnect.
• Familiarity with different onchip network topologies (ring mesh xbar etc).
• Knowledge of SystemVerilog or Verilog C or C scripting languages such as Python
• Experience with functional and performance simulators
• Knowledge of logic design principles along with timing and power implications
• Understanding of low power architecture techniques
• Understanding of high performance techniques and tradeoffs in fabric architecture

Responsibilities:

• Architecture development and specification from early highlevel architectural exploration through micro architectural direction and writing a detailed specification
• Coherent and noncoherent interconnects within the chip coherency protocol directory structure bandwidth and latency targets
• Development assessment and refinement of Architecture to target power performance area and timing goals
• Helping produce and review validation plans for functionality and performance

Education and Experience:

• PhD Masters Degree or Bachelors Degree in technical subject area.
• This is an architecture lead position so a senior level of experience is expected.