Senior Engineer Lead – DFT Engineers
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Job Location:
Santa Clarita, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
Job Title : Senior Engineer / Lead DFT Engineers
Job Location : Santa Clara CA (Onsite)
Job Type : Fulltime Position
Required Skills & Qualifications
5 years of hands-on experience in DFT and ATPG for SoC or ASIC designs
Strong understanding of DFT fundamentals including controllability observability and scan-based testing
Proven expertise in ATPG pattern generation analysis and debug
Experience with MBIST including memory test architectures and diagnostics
Knowledge of IO Test methodologies for interface and pin level validation
Solid understanding of clock DFT and clock verification concepts
Strong grasp of digital design and RTL fundamentals
Experience with industry standard DFT/ATPG EDA tools
Ability to work effectively in fast paced high performance semiconductor programs
Strong analytical problem solving and communication skills
Qualification:
BE
