Silicon Validation Manager

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Complete responsibility for management of PHY and functional Validation in post-silicon environment.

• Defining documenting executing and reporting the overall validation/test plan for Marvell switch devices

• Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality while also extending to the protocol layer of the PCIe stack.

• Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.

• Analyze and debug issues on PHY protocol of storage interface (PCIe UALink Ethernet)

• Troubleshoot failing tests with diagnostics software tools hardware analyzers oscilloscopes meters logic/protocol analyzers.

• Leading collaborative technical discussions to drive resolution on technical issues. Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY.

• Work closely with Si design engineering SW engineering and customers to address design issues and debug failure cases

What Were Looking For

• Bachelors degree in computer science Electrical Engineering or related fields and 7 years of related professional experience OR Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 5 years of experience.

• 3 years managerial experience in Silicon Validation.

• Strong understanding of high-speed SERDES equalization technique and PCIe UALink and Ethernet protocols.

• 5 years experience with High Speed IO testing debugging and validation

• Strong lab skills with hands on experience in system bring up system testing and debug.

• In-depth working knowledge of test equipment used for SERDES characterization (Scope BERT Network analyzer etc.).

• Strong analytical problem-solving and communication skills

Preferred/Plus:

• Working knowledge of PCIe interface and characterization.

• Working knowledge and experience on Ethernet and/or UALink is a definite plus.

• Extensive knowledge of the physical and protocol levels (PIPE I/F PCS MAC) of one or more common high-speed interfaces is an asset.

• Working knowledge of board design; able to read board schematics and board layout.

• Knowledge in SERDES modeling techniques Working experience with Python.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.