Chip Engineer #ESF9263

• Own and develop Die Attach and Flip Chip assembly processes end-to-end
• Drive process development optimization and yield improvement (95%)
• Work in a high-mix low-volume environment managing multiple projects simultaneously
• Design and execute DOE (Design of Experiments) for new product introductions (NPI)
• Analyze yield issues and implement process improvements on the production line
• Collaborate with cross-functional teams (Sales Ops Quality Engineering)
• Support RFQs with process inputs and technical feasibility
• Train technicians and operators on new processes and quality standards
• Contribute to advanced photonics and active alignment assembly (training provided)
• Work with or learn advanced tools like die bonders pick-and-place alignment systems

• 2 years of hands-on experience in Die Attach and Flip Chip process development
• Proven ability to develop and optimize processes with high yield (95%)
• Experience in semiconductor packaging or related micro-assembly (RF MEMS etc.)
• Strong understanding of DOE SPC and yield improvement methodologies
• Ability to multi-task in a fast-paced high-mix environment
• Exposure to equipment like ESEC/Evo Hesse Amicra FineTech Disco ficonTEC (or similar)
• Basic to intermediate exposure to software/tools (SolidWorks MATLAB Python LabVIEW)
• Background in optics/photonics is a plus (training will be provided)
• Bachelor’s degree in Engineering or related field

Must-Have

• Hands-on Die Attach (DA) & Flip Chip (FC) process development
• Strong yield improvement (SPC DOE) experience
• Ability to work in high-mix low-volume environment
• Multi-project handling & fast learning ability
• Strong ownership mindset & commitment

Nice-to-Have

• Photonics / Optoelectronics exposure or coursework
• Experience with active alignment systems
• Familiarity with advanced assembly equipment (Evo Hesse Amiga FineTech Disco ficonTEC)
• Exposure to micro-assembly (RF MEMS optics)
• Programming/tools: Python MATLAB LabVIEW SolidWorks