UFS Engineer
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Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
8 hours ago
Vacancies:
1 Vacancy
Job Summary
Job Title : UFS Engineer
Experience : 7
Location : San jose CA - Onsite
Key skills: Zebu FPGA UFS ARM
Develop and execute verification test plans for UFS host IP within a System-on-Chip (SoC) environment using tools like emulation platforms (Veloce ZEBU HAPs).
Debug failures using waveform viewers and log files to isolate and root cause issues in UFS protocols and bus interconnects
Create prepost silicon Validation C bases Test content.
Enable firmware-driven validation on emulation platforms to integrate UFS driver-level software with hardware.
Validate that UFS IP meets power performance and throughput specifications (e.g. UFS 3.x/4.x/5.x)
Capture and analyze waveforms on Zebu (or similar emulation platforms) to rootcause design and integration issues.
2 to 7 years of experience
Deep understanding of UFS standards (UFS host controller interface
Create pre/post silicon Validation C bases Test content
Strong scripting skills in Python Perl or TCL for automation
Hands-on experience with hardware emulation (Zebu/Veloce) and FPGA prototyping.
Validating how the UFS IP interacts with other SoC components including the southbridge memory controllers and bus interconnects (e.g. AXI AHB).
Identifying and fixing RTL bugs in a pre-silicon environment using waveform viewers () and log files
Ensuring the UFS IP correctly implements features like data encryption power management and high-speed data transfer (M-PHY/UniPro).
Developing performance models (often in SystemC/TLM) to analyze and optimize the storage subsystems throughput and latency.
Develop and execute test plans in C to validate the Features
Experience : 7
Location : San jose CA - Onsite
Key skills: Zebu FPGA UFS ARM
Develop and execute verification test plans for UFS host IP within a System-on-Chip (SoC) environment using tools like emulation platforms (Veloce ZEBU HAPs).
Debug failures using waveform viewers and log files to isolate and root cause issues in UFS protocols and bus interconnects
Create prepost silicon Validation C bases Test content.
Enable firmware-driven validation on emulation platforms to integrate UFS driver-level software with hardware.
Validate that UFS IP meets power performance and throughput specifications (e.g. UFS 3.x/4.x/5.x)
Capture and analyze waveforms on Zebu (or similar emulation platforms) to rootcause design and integration issues.
2 to 7 years of experience
Deep understanding of UFS standards (UFS host controller interface
Create pre/post silicon Validation C bases Test content
Strong scripting skills in Python Perl or TCL for automation
Hands-on experience with hardware emulation (Zebu/Veloce) and FPGA prototyping.
Validating how the UFS IP interacts with other SoC components including the southbridge memory controllers and bus interconnects (e.g. AXI AHB).
Identifying and fixing RTL bugs in a pre-silicon environment using waveform viewers () and log files
Ensuring the UFS IP correctly implements features like data encryption power management and high-speed data transfer (M-PHY/UniPro).
Developing performance models (often in SystemC/TLM) to analyze and optimize the storage subsystems throughput and latency.
Develop and execute test plans in C to validate the Features
Required Skills:
DATA ENCRYPTIONFPGAPERLPOWER MANAGEMENTEMULATIONLOG FILESPYTHONTCLFIRMWARE
