SoC Architecture Intern

Huaweis vision is to enrich lives through communication and intelligent innovation.

As a global leader in information and communications technology (ICT) Huawei drives innovation in artificial intelligence cloud computing and smart device technologies. Through its Carrier Enterprise and Consumer business groups the company delivers advanced Network Infrastructure Cloud and AI Platforms and industry-leading devices.

Huawei supports 45 of the worlds top 50 telecom operators and serves one-third of the global population with operations in over 170 countries and a workforce of more than 200000 employees.

Huawei Technologies Switzerland AG contributes to this innovation through cutting-edge research with offices in Zurich and Lausanne focusing on High-Performance Computing Computer Architecture Computer Vision Robotics Artificial Intelligence Neuromorphic Computing Wireless Technologies Networking and related fields.

We are a unique team of innovative diverse individuals who have come together from multiple backgrounds to create advanced Computing Architectures for communication system /Edge AI. The people who work here are generalists and we complement each other. The passion for exploring uncharted territory makes us thrive.

We seek a highly talented with research experience in the field of computing architecture. If you have technical research experience in areas such as AI computing SoC architecture heterogeneous systems cores and buses particularly with expertise in chip optimization and simulation for high performance low latency and low power consumption this is an excellent opportunity for you.

Responsibilities

• Develop novel computing architecture to improve the performance and efficiency of chip systems through software-hardware co-design and other technical innovations.

• End-to-end implementation and evaluation of new ideas and technologies in computer architecture memory system network-on-chip etc.

• Researching novel technologies in computer architecture memory/cache interconnect and/or SoC design in general to improve Performance Power efficiency and Area efficiency (PPA) system flexibility etc.

Key Qualifications

• MSc or PhD in computer science electrical engineering or related background.

• Having a strong background in hardware & software co-design microprocessor architecture for scalar/vector/tensor computing job scheduling in heterogeneous parallel systems memory optimization in many-core systems power optimization etc.

• Candidates with rich experience of using open-source tools to simulate microprocessor architecture and memory systems are preferred.

• Candidates with a good understanding of hardware-software interfaces and interactions and experience in compiler technology are preferred.

• Fluency in English both written and verbal.

Why join us:

• Collaborate with world-class scientists and engineers in an open curiosity-driven environment;

• Access to state-of-the-art technology and tools;

• Opportunities for professional growth and development;

• Last but certainly not least: be part of innovative projects that make a difference.