Director, Silicon Logical Design
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Job Summary
About Graphcore
At Graphcore were building the future of AI compute.
Were a team of semiconductor software and AI experts with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.
As part of the SoftBank Group backed by significant long-term investment we are delivering key technology into the fast-growing SoftBank AI ecosystem.
To meet the vast and exciting AI opportunity Graphcore is expanding its teams around the world.
We are bringing together the brightest minds to solve the toughest problems in a place where everyone has the opportunity to make an impact on the company our products and the future of artificial intelligence.
Job Summary
We are seeking a Director of Silicon Logical Design to lead and scale our Logical Designgroupwithin the Silicon department. This role is accountable for the overall strategy technical direction executionqualityand team development forGraphcoresmicroarchitecture and RTL design efforts.
The Director willbe responsible forensuring that our logical design methodologiesarchitecturesand RTL implementations meet worldclass standards for performance power area and schedule. This leader will partner closely with Architecture Physical Design Verification DFT and Program Managementteamsto ensure successful predictable silicon delivery aligned withGraphcoreslongterm product roadmap.
The Team
The Logical Design team deliver the micro-architecture and RTL that realise our advanced chip architectures. As Director you will guide this multi site team strengthen cross functional collaboration and drive the evolution of our design flows and capabilities.
Responsibilities and Duties
Leadership & Strategy
- Define and execute the strategic roadmap for Logical Design ensuring alignment withGraphcoressilicon and product strategy.
- Lead grow and mentor a highperformingRTL/microarchitecture design organisation.
- Establishand implementbestinclass design methodologies documentationstandardsand quality metrics.
- Drive continuous improvement across team structure workflows tooling and design processes.
Technical Ownership
- Provide technical oversight of microarchitecture specification and RTL development across all major blocks and subsystems.
- Guide architectural feasibility studies contribute to architecturaltradeoffsand microarchitecture definition.
- Oversee the integration ofthirdpartyIP complex applicationspecific blocks andhighperformancecustom designs.
- Ensure robust design signoff through highquality linting synthesis CDC/RDC timing closure and coverage metrics.
Cross-Functional Collaboration
- Partner closely with Physical Design Verification DFT Architecture and Program Managementteamsto ensure cohesive planning and execution.
- Fosterstrong communicationacross teams and global sites ensuring alignment on prioritiesrisksand deliverables.
- Support silicon bring-up and debug efforts by providing expert guidance and deep understanding of RTL behaviour and architecture.
Execution & Delivery
- Own delivery of highquality onschedule RTL for multipleparallelsilicon programs.
- Establish scalable project planning and tracking practices including resource planning and risk mitigation.
- Champion design automation and infrastructure improvements to accelerate productivity and improve design quality.
Essential Skills & Experience
- Degree in Computer Science ElectricalEngineeringor a related field; advanced degree preferred.
- Extensive experience in digital logical design micro-architecture and RTL development for large scale high performance silicon projects.
- Proven success leading and developing technical teams in a semiconductor environment.
- DeepexpertiseinSystemVerilogor VHDL and familiarity with modern digital design flows.
- Strong ability to diagnose and resolve complex design issues including via scripting/programming (PythonTcl etc.).
- Demonstrated excellence in crossfunctional leadership and communication across global teams.
- Strong organisational skills with ability to manage multiple priorities and drive execution in fast-paced environments.
Desirable Experience
- Processor or accelerator microarchitecture.
- High-speed serial interfaces and complex highbandwidth IP blocks.
- Arithmetic pipeline design and floatingpointdatapaths.
- Advanced synthesis timing analysis power analysis and logical equivalence checking.
- Design-for-test methodologies.
- Power integrity and silicondevice level understanding.
- Experience with silicon bring-up and post-silicon validation.
- Program planning and multi-project execution leadership.
Required Experience:
Director
