Silicon Photonics Integrated Circuit Design Engineer Tech Lead

Location:

We are open to candidates in the U.S. and Canada Singapore and China (Hong Kong and Shenzhen)

Depending on location and team fit this role can be remote or hybrid. Client has business presence in the U.S. Singapore China and can hire with flexibility across these regions.

About the job
Client is building advanced silicon photonics and heterogeneous photonics technologies for next-generation compute connectivity and sensing platforms. We are looking for strong builders who want meaningful technical ownership broad scope and the opportunity to help shape a core platform from an early stage.

Role Summary

Client is hiring a hands-on Silicon Photonics Integrated Circuit Engineer / Tech Lead to lead PIC device design simulation layout tapeout preparation and validation support for highly integrated photonic ICs. You will work across photonics electronics packaging and test to help deliver manufacturable devices for demanding next-generation systems.

This is a high-ownership startup role for someone who wants to move fast under uncertainty solve hard cross-functional problems and help build a path from first silicon to advanced high-volume products.

Key Responsibilities

PIC Design Integration & Co-Design

Design and optimize passive and active PIC building blocks including waveguides couplers MMIs grating couplers modulators detectors heaters and related structures.

Contribute to subsystem- and chip-level design decisions for dense photonic integration wavelength-division architectures and tightly integrated optical I/O functions.

Run photonic thermal and tolerance/yield simulations and translate results into design rules margins and practical engineering tradeoffs.

Work closely with electronics teams and external partners on ASIC/PIC co-design interfaces packaging constraints and test Verification & Tapeout Readiness

Convert schematics and design intent into DRC-clean layouts using foundry PDKs and disciplined layout practices.

Manage layout hierarchy verification flows DRC/LVS checks fill and density rules and mask readiness.

Prepare GDS and tapeout documentation packages including structures that improve debug characterization and revision speed.

Silicon Learning Validation & Productization

Define test structures test plans and acceptance criteria for first-silicon learning and design iteration.

Analyze electro-optic and optical measurement data support debug and drive model updates and design improvements.

Help build a practical path toward robust manufacturable and reliable products with attention to thermal behavior yield and scale.

Required Qualifications

Masters or PhD in Electrical Engineering Physics Photonics Optics or a related field.

5 years of hands-on integrated silicon photonics PIC development experience.

Strong understanding of device physics PIC design principles and the tradeoffs between performance manufacturability and testability.

Proficiency in photonic simulation tools such as Lumerical RSoft COMSOL or equivalent.

Experience with PDK-based layout tools such as KLayout Cadence IPKISS or equivalent.

Ability to work effectively across photonics electronics packaging and test disciplines.

Preferred Qualifications

Experience with highly integrated PICs and devices such as MRM/MZM which are used in high-speed communication optical I/O or advanced computing/connectivity systems.

Familiarity with heterogeneous integration including III-V/Si or other active-device integration approaches.

Experience related to dense WDM integration integrated light sources transceiver-class PICs such as co-packaged optics or pluggable.

MPW or production tapeout-to-silicon experience and post-silicon iteration.

Exposure to packaging thermal design reliability and the requirements of advanced-volume products.

What Success Looks Like (First 90 Days)

Understand the target platform requirements technical risks and key design tradeoffs.

Deliver or materially advance a PIC design package aligned to target specifications.

Produce a DRC-clean layout or a clear tapeout-readiness plan with risk tracking.

Define a credible test and measurement plan to accelerate learning from silicon.

Compensation

Competitive salary based on experience scope and location.

Attractive equity participation with meaningful upside for strong early hires.

Additional Information :

All your information will be kept confidential according to EEO guidelines.

Remote Work :

No

Employment Type :

Full-time