Principal Design Verification Engineer

About the Team

The Digital Engineering group is a highly collaborative organization comprising experienced ASIC and Systems engineers with deep expertise across architecture logic design verification physical design hardwaresoftware cosimulation FPGA prototyping and firmware development. The team brings together decades of cumulative industry experience and operates at the forefront of modern semiconductor design.

We leverage advanced semiconductor process technologies and industrystandard stateoftheart EDA tools to deliver highquality silicon solutions. Our scope spans the full SoC development lifecycle from architectural definition through verification validation and final product delivery.

Senior/Staff ASIC Verification Engineer

(Typically 1012 years of industry experience)

Responsibilities

• Lead verification efforts for complex IPs or subsystems contributing to SoClevel verification strategy under guidance from principal/architectlevel engineers.
• Design develop and maintain SystemVerilog/UVMbased verification environments including agents scoreboards monitors checkers assertions and functional coverage.
• Contribute to verification planning translating architectural specifications into detailed test plans and coverage models and ensuring alignment with overall project verification goals.
• Develop UVM test sequences including constrainedrandom directed and layered sequences and participate in defining stimulus strategies to achieve coverage closure.
• Drive verification closure for owned blocks tracking functional code assertion and power coverage identifying gaps and proposing corrective actions.
• Participate in lowpower verification flows including UPF/CPF integration and validation of power states and transitions at block and subsystem levels.
• Support HWFW coverification activities including development of C/C testcases for simulation emulation or FPGA prototyping and assist with early firmware bringup.
• Debug complex RTL and gatelevel issues working closely with design and architecture teams to rootcause functional timing and powerrelated problems.
• Contribute to regression infrastructure including test triage failure analysis and improving regression efficiency and stability.
• Collaborate effectively with crossfunctional teams (design firmware validation and architecture) to ensure timely and highquality delivery.
• Mentor junior verification engineers providing technical guidance code reviews and bestpractice recommendations.

Qualifications / Skills

• Strong track record of block or subsystem verification ownership with experience contributing to multiple successful tapeouts.
• Advanced proficiency in SystemVerilog and UVM with handson experience building reusable and maintainable verification components.
• Solid understanding of ASIC verification methodologies including:
  • Verification planning and execution
  • Directed and constrainedrandom testing
  • Functional code and assertion coverage
  • Assertionbased verification
  • Lowpower verification using UPF/CPF
• Experience with C/Cbased test development for HWFW simulation emulation or prototyping environments.
• Working knowledge of scripting languages such as Python or Perl for automation debug and regression support.
• Familiarity with standard development and tracking tools including Git Jira and Confluence.
• Strong analytical and debugging skills with the ability to work independently on complex verification problems.
• Clear communication skills and a collaborative mindset capable of influencing technical decisions within the immediate team.

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