RET OPC Modeling Engineer
Share
Job Location:
Dallas, IA - USA
Monthly Salary:
Not Disclosed
Posted on:
7 hours ago
Vacancies:
1 Vacancy
Department:
Job Summary
Change the world. Love your job.
A Process Development Engineer is responsible for the development characterization and optimization of MEMS resonator devices to meet the requirements for volume production as part of the analog technology development team. The ideal candidate will be a technical leader in the area of resonators and oscillators driving the characterization and optimization of the device and process to insure robustness reliability and manufacturability meeting all electrical device performance targets.
As a Resolution Enhancement Techniques (RET) modeling engineer youll create and optimize OPC models for Texas Instruments most advanced technology nodes. Models will include both lithography and etch-based models. Responsibilities will include but are not limited to:
- Partnering with design process engineering and process integration teams to define design shapes needed for building accurate models.
- Designing parameterized mask layouts needed for model building inputs.
- Investigating and implementing ML and AI methods for improving model accuracy and runtime.
- Implementing advanced optimization techniques.
- Working with process engineering and process integration teams on wafer verification to validate model quality.
- Working with OPC verification engineers to improve the accuracy of post-OPC verification models. These include but are not limited to weak image assist feature printing and resist top-loss models.
Qualifications
Minimum requirements:
- Masters in Electrical Engineering Physics Computer Science Chemistry or related degree.
- 8 years experience in OPC modeling in advanced node lithography.
- Expertise in selecting and optimizing the features needed for properly sampling design spaces for building accurate models.
- Expertise in developing test requirements to validate OPC modeling solutions.
- Strong knowledge/understanding of advanced lithography simulation and RET techniques used in semiconductor manufacturing and process development.
Preferred qualifications:
- Ability to lead and drive advanced processes associated with double patterning techniques in 22 nm node development.
- Expertise in Synopsys ProGen modeling software.
- Demonstrated knowledge of OPC verification software packages such as ORC LMC or PLRC.
- Knowledge of critical care-abouts for 28 and 22 nm node processing.
- Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software such as Cadence Virtuoso or KLayout.
- Programming experience in Unix environment.
- Understanding of OPC pattern validation methodologies and process window assessment techniques like KLAs Photolithography Wafer Qualification (PWQ).
- Demonstrated strong analytical and problem solving skills.
- Strong verbal and written communication skills.
Required Experience:
IC
Key Skills
About Company
Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation ... View more
