DFT Engineer

DFT engineers will be responsible for DFT architecture and test methodology definition and driving implementation primarily for Scan-based (ATPG) testing of high-end SoCs. These candidates likely lead a team DFT design and ATPG engineers and programmers to define DFT structures and tool flows needed for testing next-generation high-end server SoC products and drive their successful addition to work within a DFT team these candidates will work with hardware design teams to ensure successful implementation of various DFT structures in RTL and they will work with SoC implementation teams on synthesis physical design clocking timing and design verification.

These candidates will also work with Product and Test Engineering (PTE) teams to drive successful bring-up of test vectors on ATE platforms. This role will span from current to future SoC products and as such candidate activities will include strategy design methodology and test execution. These candidates will interface with internal tool development teams and will be responsible for driving synergies that facilitate test insertion clock design and vector development automation. Finally these candidates will work with tool vendors such as Mentor Graphics and Synopsys to define and integrate tool capabilities (particularly DFT insertion and ATPG) needed to implement and roll out DFT strategies.

Responsibilities include: Test strategy definition DFT Architecture for large multi-core server chips Logic specification and RTL design of DFT IP Software specification DFT team leadership of related activities ATPG test planning (including coverage test time test memory footprint on ATE Coordinates cross-functional front-to-back SoC implementation and verification of DFT structures) and Bring-up of ATPG patterns on ATE.

3 years of experience in the following technical areas :

• Defining and executing DFT-related tool flows spanning insertion ATPG as well as DFT requirements in front-to-back SoC implementation flows
• Test vector planning for bring-up and production and hand-on ATE bring-up experience
• Achieving high coverage via SAF TDF as well as knowledge of other techniques such as Small Delay Defects Path testing LOC/LOS etc.
• Tessent DFTC TCL/PERL IEEE 1149 and 1687 Primetime SpyGlass Verilog simulation including SDF and Advantest ATE
• Architecting automation strategies that align with third party DFT tools and creating further efficiencies
• Leading large DFT/ATPG teams
• Defining/bring-up of DFT architecture including hierarchical core/chip based flows and pattern retargeting
• Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing

• Required : Bachelors in Computer Engineering Computer Science Electrical Engineering and/or related field
• Preferred : Masters in Computer Engineering Computer Science Electrical Engineering and/or related field