Job Title: ASIC Power Engineer
Duration: 6 Months
Work Location: Sunnyvale CA (Hybrid US)
Job Overview
We are seeking an experienced ASIC Power Engineer to perform power analysis and optimization for advanced semiconductor designs with a focus on AR/VR technologies. The role involves working across RTL to physical design stages with opportunities to contribute to machine learningrelated workflows.
Key Responsibilities
- Perform PPA (Power Performance Area) optimization using industry-standard tools such as Fusion Compiler
- Conduct RTL and gate-level power analysis
- Analyze and process report/log files for data extraction transformation and insights
- Setup run debug and analyze ASIC design flows including synthesis place & route timing and power
- Develop scripts for automation data analysis and reporting
- Implement design blocks at RTL and define power intent using UPF
- Document workflows methodologies and results clearly
Minimum Qualifications
- 10 years of experience as an ASIC Power Engineer CAD Engineer or Physical Design Engineer
- Hands-on experience with power estimation synthesis and some exposure to physical design
- Strong understanding of power trade-offs in chip design and backend implementation
- Proficiency in scripting and data analysis
- Bachelors degree in Electrical Engineering Computer Science or equivalent experience
Preferred Qualifications
- Experience with Synopsys tools (DC ICC PrimeTime PX / PrimePower VCS Verdi) and/or Cadence tools (Joules)
- Strong programming skills in Python Perl or similar scripting languages
- Experience with Excel or MATLAB for data analysis modeling and visualization
- Knowledge of low-power design methodologies and UPF-based power intent specification
- Experience in silicon power characterization
- Familiarity with power profiling at IP and SoC levels
For more details reach at
Required Experience:
IC
Job Title: ASIC Power Engineer Duration: 6 Months Work Location: Sunnyvale CA (Hybrid US)Job OverviewWe are seeking an experienced ASIC Power Engineer to perform power analysis and optimization for advanced semiconductor designs with a focus on AR/VR technologies. The role involves working across R...
Job Title: ASIC Power Engineer
Duration: 6 Months
Work Location: Sunnyvale CA (Hybrid US)
Job Overview
We are seeking an experienced ASIC Power Engineer to perform power analysis and optimization for advanced semiconductor designs with a focus on AR/VR technologies. The role involves working across RTL to physical design stages with opportunities to contribute to machine learningrelated workflows.
Key Responsibilities
- Perform PPA (Power Performance Area) optimization using industry-standard tools such as Fusion Compiler
- Conduct RTL and gate-level power analysis
- Analyze and process report/log files for data extraction transformation and insights
- Setup run debug and analyze ASIC design flows including synthesis place & route timing and power
- Develop scripts for automation data analysis and reporting
- Implement design blocks at RTL and define power intent using UPF
- Document workflows methodologies and results clearly
Minimum Qualifications
- 10 years of experience as an ASIC Power Engineer CAD Engineer or Physical Design Engineer
- Hands-on experience with power estimation synthesis and some exposure to physical design
- Strong understanding of power trade-offs in chip design and backend implementation
- Proficiency in scripting and data analysis
- Bachelors degree in Electrical Engineering Computer Science or equivalent experience
Preferred Qualifications
- Experience with Synopsys tools (DC ICC PrimeTime PX / PrimePower VCS Verdi) and/or Cadence tools (Joules)
- Strong programming skills in Python Perl or similar scripting languages
- Experience with Excel or MATLAB for data analysis modeling and visualization
- Knowledge of low-power design methodologies and UPF-based power intent specification
- Experience in silicon power characterization
- Familiarity with power profiling at IP and SoC levels
For more details reach at
Required Experience:
IC
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