Sr. DFT Engineer
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Job Summary
Senior DFT Engineer: You will be responsible for designing implementing and verifying DFT architectures for complex SoCs. You will work closely with RTL physical design and verification teams to ensure robust testability and high-quality silicon.
Key Responsibilities
-Define and implement DFT architecture for SoCs (scan MBIST LBIST boundary scan).
-Develop and integrate scan insertion test compression and ATPG patterns.
-Implement memory BIST and logic BIST strategies.
-Collaborate with RTL and physical design teams for DFT insertion and timing closure.
-Perform DFT verification at RTL and gate-level simulations.
-Work with ATE teams for test program development and silicon bring-up.
-Optimize test coverage pattern count and test time.
Required Skills
-Strong expertise in DFT methodologies: Scan MBIST LBIST JTAG.
-Hands-on experience with industry standard ATPG tools.
-Proficiency in UPF/CPF-based low-power DFT.
-Knowledge of fault models (stuck-at transition path delay).
-Familiarity with physical design constraints for DFT.
-Experience in silicon debug and ATE bring-up.
Preferred Qualifications
- Pas experience with SoC level DFT
-Exposure to high-speed interfaces and DFT for mixed-signal blocks.
-Strong problem-solving and communication skills.
Education
-Bachelors or Masters in Electrical/Electronics Engineering.
#LI-7013Required Experience:
Senior IC
Key Skills
About Company
NXP is a global semiconductor company creating solutions that enable secure connections for a smarter world.
