Principal Engineer Physical Design

Heres a job description for a Principal Engineer - Physical Design at NXP India Pvt. Ltd. - Noida:

Principal Engineer - Physical Design

Company:** NXP India Pvt. Ltd. - Noida

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Job Summary

We are seeking a highly experienced Principal Engineer specializing in Physical Design to lead and drive complex physical design activities for cutting-edge semiconductor products. This role involves taking ownership of full chip or major block physical implementation ensuring successful tape-out within aggressive schedules and mentoring junior engineers.

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Job Responsibilities

* Lead and execute all aspects of physical design for complex digital blocks and/or full chip designs from RTL-to-GDSII including floorplanning power planning place and route clock tree synthesis (CTS) timing closure (STA) signal integrity (SI) analysis and physical verification (DRC/LVS/ERC).
* Drive and optimize design methodologies and flows for power performance and area (PPA) targets.
* Collaborate closely with RTL design DFT and CAD teams to define design constraints resolve issues and ensure seamless integration.
* Develop and implement innovative solutions to overcome physical design challenges in advanced technology nodes.
* Perform comprehensive timing analysis and develop strategies to achieve difficult timing closure targets at block and full-chip levels.
* Conduct power integrity (IR drop EM) analysis and implement solutions for robust power delivery networks.
* Responsible for sign-off quality physical verification and ensuring designs meet all foundry rules.
* Participate in definition and review of design specifications PPA targets and project schedules.
* Mentor and provide technical guidance to junior physical design engineers fostering their growth and development.
* Stay updated with industry trends new tools and methodologies in physical design.

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Job Qualifications

* Bachelors or Masters degree in Electrical/Electronics Engineering or a related field.
* 10 years of hands-on experience in physical design of complex SoCs or ASICs in advanced technology nodes (e.g. 16nm 7nm 5nm).
* Expert-level proficiency with industry-standard physical design tools (e.g. Synopsys Fusion Compiler/Innovus Cadence Genus/Tempus PrimeTime ICC2).
* Strong expertise in static timing analysis (STA) and timing closure techniques.
* In-depth understanding of deep sub-micron design challenges including signal integrity power integrity and DFM issues.
* Proven experience in floorplanning power grid design and clock tree synthesis.
* Solid understanding of physical verification concepts and tools (DRC LVS ERC).
* Proficiency in scripting languages (Tcl Perl Python) for automation and flow development.
* Excellent problem-solving analytical and debugging skills.
* Strong communication and interpersonal skills with the ability to lead and collaborate effectively within a global team.
* Prior experience in mentoring junior engineers is highly desirable.

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