SeniorStaff ATE Test Engineer
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Job Location:
Irvine, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
14 hours ago
Vacancies:
1 Vacancy
Job Summary
Senior Staff Test Engineer Mixed Signal / DSP Products
Location: Irvine CA
Role Overview:
As a Senior Staff Test Engineer you will lead test development and manufacturing readiness for next-generation DSP and mixed-signal SoCs. You will own the complete test strategyfrom first silicon bring-up through high-volume productioncollaborating closely with design validation systems and manufacturing teams. This highly hands-on leadership role carries broad technical influence driving test architecture definition methodology development and scalable ATE solutions that optimize product quality yield and cost.
Key Responsibilities:
Technical Ownership:
Own test engineering solutions across all product phases: silicon bring-up characterization customer sampling qualification and high-volume manufacturing.
Test Architecture & Strategy:
Define test strategy coverage goals and manufacturing methodologies; develop comprehensive product Test Plans and drive DFT alignment.
ATE Solution Development:
Implement all aspects of product test development including: ATE configuration Test software and automation Test hardware including probe cards load boards fixturing and mechanical interfaces
Cross-Functional Collaboration:
Act as a core team member for new product introduction participating in architecture reviews testability/DFT reviews to achieve quality and cost requirements.
Coverage & Optimization:
Partner with Design Engineering to ensure test coverage yield optimization and test time targets.
Correlation & Characterization:
Correlate ATE results with bench validation data; characterize device performance and margins for volume production.
Manufacturing Readiness:
Coordinate with manufacturing technology and sub-con partners to drive NPI test release and volume ramp.
Mentorship & Influence:
Provide technical guidance and help shape long-term test infrastructure and standards.
Required Qualifications:
BSEE MSEE (preferred) or related field with 10 years of test engineering experience
Deep expertise with Advantest V93000 (93k) and/or Teradyne UltraFLEX (UFLEX) platforms
Strong background in mixed-signal ATE development for complex SoCs including: High-speed ADC/DAC SerDes DSP-based devices
Solid understanding of Scan MBIST and loop-back test methodologies
Preferred Qualifications:
Familiarity with bench instrumentation such as Network Analyzers and Sampling Oscilloscopes
At-speed wafer probe experience
Experience with schematic capture PCB layout and 2D/3D CAD tools
Location: Irvine CA
Role Overview:
As a Senior Staff Test Engineer you will lead test development and manufacturing readiness for next-generation DSP and mixed-signal SoCs. You will own the complete test strategyfrom first silicon bring-up through high-volume productioncollaborating closely with design validation systems and manufacturing teams. This highly hands-on leadership role carries broad technical influence driving test architecture definition methodology development and scalable ATE solutions that optimize product quality yield and cost.
Key Responsibilities:
Technical Ownership:
Own test engineering solutions across all product phases: silicon bring-up characterization customer sampling qualification and high-volume manufacturing.
Test Architecture & Strategy:
Define test strategy coverage goals and manufacturing methodologies; develop comprehensive product Test Plans and drive DFT alignment.
ATE Solution Development:
Implement all aspects of product test development including: ATE configuration Test software and automation Test hardware including probe cards load boards fixturing and mechanical interfaces
Cross-Functional Collaboration:
Act as a core team member for new product introduction participating in architecture reviews testability/DFT reviews to achieve quality and cost requirements.
Coverage & Optimization:
Partner with Design Engineering to ensure test coverage yield optimization and test time targets.
Correlation & Characterization:
Correlate ATE results with bench validation data; characterize device performance and margins for volume production.
Manufacturing Readiness:
Coordinate with manufacturing technology and sub-con partners to drive NPI test release and volume ramp.
Mentorship & Influence:
Provide technical guidance and help shape long-term test infrastructure and standards.
Required Qualifications:
BSEE MSEE (preferred) or related field with 10 years of test engineering experience
Deep expertise with Advantest V93000 (93k) and/or Teradyne UltraFLEX (UFLEX) platforms
Strong background in mixed-signal ATE development for complex SoCs including: High-speed ADC/DAC SerDes DSP-based devices
Solid understanding of Scan MBIST and loop-back test methodologies
Preferred Qualifications:
Familiarity with bench instrumentation such as Network Analyzers and Sampling Oscilloscopes
At-speed wafer probe experience
Experience with schematic capture PCB layout and 2D/3D CAD tools
Required Experience:
Staff IC
Key Skills
- Continuous Integration
- Jenkins
- Test Cases
- Performance Testing
- C/C++
- LabView
- Jira
- Software Testing
- System Testing
- Test Automation
- Selenium
- Cerner
