Physical Design Engineer (PNRPhysical VerificationSTAEMIR)
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Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate will have the opportunity to work on many varieties of challenging designs i.e. low power and high speed design. As well as participating in or leading next generation PHY IP physical design methodology and flow development the candidate will work closely with our RTL design team & Analog Team to ensure successful tapeouts.
Main Job Tasks and Responsibilities:
-Participating in or leading next-generation physical design methodology and flow development in advanced technology nodes.
-Perform physical design implementation including floor planning power grid design place and route clock tree synthesis timing closure power/signal integrity signoff physical verification (DRC/LVS/Antenna) EM/IR signoff DFM Closure.
Position Requirements:
- Bachelor or above degree in majors of EE/CS/IT with 5 years work experience
- Extensive knowledge of the design rule for the process of N7/N5 and below
- Knowledge of scripting languages and use in methodology
- Ability of fixing the physical design violations including: DRC DFM LVS ANT ERC etc.
- Deep experience of static timing analysis
- Ability to learn quickly
- High level of communication and teamwork
- Carefulness responsibility and persistence
Were doing work that matters. Help us solve what others cant.
We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process we encourage you to make your needs known.
Required Experience:
IC
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About Company
Do you want to shape the future of technology? Cadence is leading the charge to solve some of technology’s toughest challenges. We work with the world’s most innovative companies, across a growing range of industries. Major trends that you hear about everyday – like artificial intell ... View more
