Senior Staff Digital Design Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Collaborate with systems and architecture teams to define SoClevel specifications including performance power area feature requirements and DSP/datapath architectural considerations.

Translate highlevel product and protocol requirements into detailed microarchitecture specifications for complex subsystems highspeed datapaths DSP pipelines and IP blocks.

Own RTL development for assigned blocks delivering highquality synthesizable SystemVerilog RTL that meets functionality performance and power targets.

Implement and drive the full ASIC frontend design flow including lint CDC/RDC synthesis timing constraint development and designfortest readiness.

Partner with STA and PNR teams to support timing closure floorplanning congestion analysis and design optimizations across advanced process nodes.

Lead integration of digital logic into larger subsystems and toplevel assemblies ensuring clean interfaces modularity and reusability.

Develop scalable and maintainable design components including parameterized datapaths DSP building blocks and reusable infrastructure logic.

Work closely with DV teams to define verification strategies review test plans and ensure functional coveragedriven and poweraware validation of the design.

Support presilicon validation including emulation FPGA prototyping and performance modeling of highspeed datapaths and DSP algorithms.

Drive postsilicon bringup and debug collaborating with lab and systems teams to validate functionality characterize performance and resolve complex issues across datapath DSP and protocol layers.

Participate in detailed design and microarchitecture reviews contributing to continuous improvement of design verification and methodology flows.

What Were Looking For

• Extensive experience in digital ASIC design including microarchitecture development RTL implementation (SystemVerilog preferred) and integration of complex logic blocks.
• 10 years of industry experience working on largescale ASICs for networking datacenter connectivity or highbandwidth compute architectures.
• Strong background in highperformance DSP and highspeed datapath design including pipelined arithmetic units algorithmdriven hardware implementation packet processing engines memory subsystems and largescale control/state machines.
• Familiarity with Ethernet protocols and networking standards including MAC PCS framing flow control and packetlevel behaviors.
• Proficiency with frontend design flows including lint CDC/RDC synthesis STA and power/performance optimization.
• Demonstrated ability to collaborate across architecture verification physical design firmware and systems teams driving designs from concept through tapeout.
• Strong debug skills across RTL simulation emulation FPGA prototypes and silicon bringup.
• Familiarity with advanced process nodes (5nm 3nm or similar) and their implications for timing power and signal integrity.
• Excellent communication and leadership skills with experience mentoring junior engineers and influencing technical direction.
• BS/MS in Electrical Engineering Computer Engineering or related field; PhD is a plus.

Preferred / Plus Skills

• Advanced highspeed DSP algorithm implementation including adaptive equalization (FFE DFE CTLE) channel estimation and highthroughput filtering architectures.
• Experience with FEC architectures such as LDPC RS BCH or other highspeed coding/decoding schemes used in networking and optical interconnects.
• Previous PHY design experience including PMAlevel DSP pipelines equalization blocks clock recovery and SerDesadjacent logic.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.