FPGA Design Verification Engineer
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Job Location:
Monthly Salary:
Posted on:
7 hours ago
Vacancies:
1 Vacancy
Job Summary
Details:
Stefanini Group is hiring!
Stefanini is looking for FPGA Design Verification Engineer -Ottawa Ontario Canada
For quick apply please contact Ph:
W2 Only!
22 Days PTO (See Below the bifurcation)
* 10 Days PTO( 80 Hours of PTO - Accrual Basis)
* 9 Holidays on average throughout the year
* 3 Personal Days
About the Role:
Clients 5G R&D team is developing next-generation Open RAN Radio Units for 4G and 5G networks. As an FPGA Design Verification Engineer you will play a key role in ensuring the functional correctness robustness and quality of FPGA-based designs used in high-performance wireless systems.
You will own verification activities for FPGA IP and subsystems work closely with FPGA designers and system teams and help define and deploy AI-assisted verification workflows to improve productivity and coverage in complex designs.
What Youll Do
Design Verification & Validation:
Own and drive verification plans for FPGA IP and subsystems used in 4G/5G Radio Units.
Design implement and maintain SystemVerilog / UVM verification environments.
Develop constrained-random tests assertions and scoreboards.
Run debug and analyze simulations using Synopsys VCS.
Analyze functional code and assertion coverage and close coverage gaps.
Perform independent root-cause analysis of RTL and system-level issues.
Clients 5G R&D team is developing next-generation Open RAN Radio Units for 4G and 5G networks. As an FPGA Design Verification Engineer you will play a key role in ensuring the functional correctness robustness and quality of FPGA-based designs used in high-performance wireless systems.
You will own verification activities for FPGA IP and subsystems work closely with FPGA designers and system teams and help define and deploy AI-assisted verification workflows to improve productivity and coverage in complex designs.
What Youll Do
Design Verification & Validation:
Own and drive verification plans for FPGA IP and subsystems used in 4G/5G Radio Units.
Design implement and maintain SystemVerilog / UVM verification environments.
Develop constrained-random tests assertions and scoreboards.
Run debug and analyze simulations using Synopsys VCS.
Analyze functional code and assertion coverage and close coverage gaps.
Perform independent root-cause analysis of RTL and system-level issues.
AI-Assisted Verification Workflow:
Help define and operationalize AI-driven DV workflows.
Identify opportunities to apply AI to:
o Testbench and test generation
o Intelligent stimulus creation
o Log analysis and failure triage
o Coverage analysis and closure
Evaluate effectiveness of AI-assisted approaches and refine workflows.
Contribute to documentation and best practices for AI-enabled DV.
Help define and operationalize AI-driven DV workflows.
Identify opportunities to apply AI to:
o Testbench and test generation
o Intelligent stimulus creation
o Log analysis and failure triage
o Coverage analysis and closure
Evaluate effectiveness of AI-assisted approaches and refine workflows.
Contribute to documentation and best practices for AI-enabled DV.
Collaboration & Integration:
Work closely with FPGA designers to review specifications interfaces and corner cases.
Act as a verification partner during design reviews and architecture discussions.
Collaborate with system radio and software teams to ensure end-to-end correctness.
Support integration regression and system-level verification activities.
Work closely with FPGA designers to review specifications interfaces and corner cases.
Act as a verification partner during design reviews and architecture discussions.
Collaborate with system radio and software teams to ensure end-to-end correctness.
Support integration regression and system-level verification activities.
Automation & Infrastructure:
Develop and maintain DV automation for simulations regressions and reporting.
Use scripting to orchestrate large regression runs and analyze results.
Improve verification efficiency through tooling scripting and process improvements.
Develop and maintain DV automation for simulations regressions and reporting.
Use scripting to orchestrate large regression runs and analyze results.
Improve verification efficiency through tooling scripting and process improvements.
#LI-PG1
#LI-ONSITE
Details:
What Youll Bring:
Essential Requirements:
Bachelors degree in Electrical Engineering Computer Engineering or related field.
3 years of experience in FPGA or ASIC design verification.
Experience verifying FPGA designs for wireless or high-speed systems.
Strong proficiency in SystemVerilog and simulation-based verification.
Hands-on experience with UVM methodology.
Strong debug skills and understanding of RTL design principles.
Experience using Synopsys VCS or equivalent simulators.
Proficiency with Git/GitHub and collaborative workflows.
Experience with scripting for DV automation including Shell Scripting (Bash).
Interest in or experience with AI/ML-assisted verification techniques.
Essential Requirements:
Bachelors degree in Electrical Engineering Computer Engineering or related field.
3 years of experience in FPGA or ASIC design verification.
Experience verifying FPGA designs for wireless or high-speed systems.
Strong proficiency in SystemVerilog and simulation-based verification.
Hands-on experience with UVM methodology.
Strong debug skills and understanding of RTL design principles.
Experience using Synopsys VCS or equivalent simulators.
Proficiency with Git/GitHub and collaborative workflows.
Experience with scripting for DV automation including Shell Scripting (Bash).
Interest in or experience with AI/ML-assisted verification techniques.
Desirable Skills
Familiarity with LTE 5G NR CPRI/eCPRI PTP or O-RAN architectures.
Knowledge of AXI Ethernet PCIe JESD204B/C and high-speed SERDES.
Experience with Python and TCL for verification automation.
Exposure to system-level or FPGA-in-the-loop verification.
Why Join Us:
Work on production-grade 5G Radio Units with global deployment.
Be part of a team shaping AI-assisted verification workflows in real products.
Collaborate with experienced FPGA wireless and system architects.
Opportunity to grow into Senior DV FPGA Design or Technical Lead roles.
Contribute to our innovation and intellectual property in wireless infrastructure.
Familiarity with LTE 5G NR CPRI/eCPRI PTP or O-RAN architectures.
Knowledge of AXI Ethernet PCIe JESD204B/C and high-speed SERDES.
Experience with Python and TCL for verification automation.
Exposure to system-level or FPGA-in-the-loop verification.
Why Join Us:
Work on production-grade 5G Radio Units with global deployment.
Be part of a team shaping AI-assisted verification workflows in real products.
Collaborate with experienced FPGA wireless and system architects.
Opportunity to grow into Senior DV FPGA Design or Technical Lead roles.
Contribute to our innovation and intellectual property in wireless infrastructure.
Stefanini takes pride in hiring top talent and developing relationships with our future employees. Our talent acquisition teams will never make an offer of employment without having a phone conversation with you. Those face-to-face conversations will involve a description of the job for which you have applied. We also speak with you about the process including interviews and job offers.
About Stefanini Group:
The Stefanini Group is a global provider of offshore onshore and near shore outsourcing IT digital consulting systems integration application and strategic staffing services to Fortune 1000 enterprises around the world. Our presence is in countries like the Americas Europe Africa and Asia and more than four hundred clients across a broad spectrum of markets including financial services manufacturing telecommunications chemical services technology public sector and utilities. Stefanini is a CMM level 5 IT consulting company with a global presence. We are CMM Level 5 company
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