mid-level Design Verification Engineer
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Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
22 hours ago
Vacancies:
1 Vacancy
Job Summary
Our client a leading technology organization specializing in high-end networking products is seeking a Verification Eng to join their team. As a Verification Eng you will be part of the Engineering Department supporting FPGA verification projects. The ideal candidate will demonstrate strong technical expertise proactive problem-solving skills and excellent collaboration abilities which will align successfully in the organization.
Whats the Job
- Own verification of entire FPGA design used in high-end router products
- Understand design specifications and collaborate with design engineers to identify verification scenarios
- Create test plans develop constrained-random verification environments and generate test cases regressions and coverage reports
- Identify and implement coverage measures for stimulus and corner-case scenarios
- Develop object-oriented testbench infrastructure BFMs and test cases in UVM
Whats Needed
- Strong academic background in Electrical Engineering (Bachelors required Masters preferred)
- 7-10 years of verification experience in ASIC/FPGAs
- Proficiency in SystemVerilog with clear OOP concepts
- Experience developing verification environments including UVM BFMs and test cases
- Knowledge of PCIe Ethernet and slow-speed interfaces like I2C SPI MDIO
Whats in it for me
- Opportunity to work on cutting-edge FPGA verification projects
- Collaborate with a talented and innovative engineering team
- Gain valuable experience in high-performance networking hardware
- Work in a dynamic and supportive environment
- Long-term contract with potential for growth and development
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
