Lead Design Engineer

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality.

Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Lead Design Engineer

Location: Warszawa Poland

Reports to: Design Engineering Architect

Job Overview:

The Lead Design Verification Engineer will take a technical leadership role in digital design verification with endtoend ownership of verification activities from concept and architecture definition through coverage closure and signoff.

The role includes verification planning testbench architecture functional verification debug and metricdriven closure as well as mentoring engineers and influencing verification methodology and quality.

Job Responsibilities:

• Lead and contribute to digital design verification architecture for complex IP blocks.
• Define and own verification plans (vPlan / test plan) aligned with specifications and quality goals.
• Architect and implement SystemVerilog / UVMbased verification environments.
• Develop and review assertions (SVA) for protocol checking design intent and signoff readiness.
• Drive functional coverage definition coverage analysis and coverage closure.
• Perform debug and rootcause analysis across RTL testbench and simulation results.
• Ensure complete verification and signoff readiness including metrics reviews and documentation.
• Collaborate closely with design architecture and crosssite teams.
• Mentor and technically guide junior verification engineers.
• Contribute to continuous improvement of verification methodologies flows and best practices.

Job Qualifications:

• BS MS pr PhD in Electrical Engineering Computer Engineering or Computer Science.
• 7 years of experience in digital design verification or semiconductor IP development.
• Strong handson experience with SystemVerilog UVM and assertionbased verification (SVA).
• Proven experience in verification planning coveragedriven verification and coverage closure.
• Solid understanding of full verification flow from concept through signoff.
• Strong debugging analytical and problemsolving skills.
• Working knowledge of UNIX/Linux environments scripting and automation.
• Effective communication skills and ability to work in distributed / remote teams.
• Teamoriented mindset fluent in English.
• Must be legally eligible to work in Poland.

Additional Skills/Preferences:

• Experience with metricdriven verification and signoff methodologies.
• Exposure to formal verification and/or lowpower CDC or lint flows.
• Knowledge of processorbased systems and embedded software interaction.
• Semiconductor IP development or FPGA design experience.
• Working knowledge of industrystandard protocols (e.g. PCIe CXL AMBA AXI USB).
• Understanding of cryptographic algorithms and securityrelated verification is a plus.
• Experience influencing verification quality methodology or best practices at team or project level.

Check what we can offer you:

• Competitive salary
• Copyrights tax relief procedure implemented in salary calculations
• Flexible working hours
• Officebased / hybrid work model
• Continuous professional development: trainings and seminars
• Employee Stock Purchase Plan bonuses and stock programs
• Private medical care
• Life insurance
• Multisport Plus cards
• Social Fund benefits
• The opportunity to work for a Great Place to Work & Fortune 100 organization

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

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