Sr Staff Engineer DFT

Bengaluru - India

Monthly Salary: Not Disclosed

Posted on: 2 days ago

Vacancies: 1 Vacancy

Job Summary

The Principal DFT Engineer serves as a technical authority and strategic lead in designing and deploying industry-leading Design-for-Test (DFT) architectures. This role is responsible for the end-to-end DFT strategy for complex high-performance SoCsspanning architectural definition advanced ATPG/MBIST/LBIST strategies and silicon lifecycle management. You will drive innovation in test methodology to achieve world-class quality minimize Test Cost (CoT) and ensure seamless transition from pre-silicon RTL to high-volume manufacturing (HVM).

About GlobalFoundries

GlobalFoundriesis a leading full-service semiconductor foundry providing a unique combination of design development and fabrication services to some of the worlds most inspired technology companies. With a global manufacturing footprint spanning three continents GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information visit.

Your Job

Architectural Leadership:Define and own the global DFT architecture including Hierarchical Scan Compressed ATPG Memory BIST/Repair (BISR) Logic BIST and IEEE 1687 (IJTAG) networks for multi-die orchiplet-based designs.

Test Strategy Optimization:Develop advanced strategies for defect-oriented testing (Cell-aware Slack-aware) andoptimizepattern volumes to balance aggressive coverage targets with tester memory constraints.

Cross-Functional Integration:Lead the integration of DFT requirements into RTL Synthesis and Physical Design (STA/PD) flows. Drive Design for Manufacturability (DFM) initiatives to improve yield.

Silicon Bring-up & Debug:Spearhead post-silicon validation and silicon bring-up. Own the root-cause analysis of complex test failures and provide expert-level debugging of ATE/System-level failures.

Methodology & Automation:Architect andmaintainscalable high-performance DFT flows using TCL Python or Perl. Evaluate and benchmark emerging EDA tool features to stay ahead of technology nodes (5nm/3nm and beyond).

Mentorship & Influence:Provide technical mentorship to junior and senior engineers. Act as a consultant for verification and backend teams to resolve bottleneck timing or routing issues caused by DFT structures.

Technical Documentation:Author comprehensive DFT specifications and strategy documents that serve as the Gold Standard for current and future project iterations.

Other Responsibilities

Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Securityrequirementsand programs.

Required Qualifications

Education:Bachelors Masters in Electrical Engineering Computer Engineering or related fields.

Experience:8 yearsof hands-on DFT experience with a proventrack recordof successfully taping out multiple complex SoCs.

Tool Mastery:Expert-levelproficiencywith industry-standard EDA suites (e.g.SynopsysTestMAX/DFTMAX Cadence Modus or Siemens/MentorTessent).

Advanced Logic Knowledge:Deep understanding of scan compression architectures (EDT/Adaptive Scan) hierarchical DFT and mixed-signal test integration.

Scripting:Advancedproficiencyin TCL and Python/Perl for developing custom CAD attributes and automating complex EDA flows.

Problem Solving:Demonstratedability to solve showstopper timing closure issues related to DFT or complex ATPG coverage gaps.

Preferred Qualifications

Specialized Flows:Experience withAutomotive ASIL-Dfunctional safety requirements including In-System Test (IST) and periodic logic/memory monitoring.

Yield Analysis:Experience with Volume Diagnostics and Yield Learning tools to drive DPPM reduction.

Industry Presence:Active participation in technical conferences or a history of contributing to patented DFT innovations.

GlobalFoundries is an equal opportunity employer cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity efficiency and innovation whilst our employees feel truly respected valued and heard.

As an affirmative employer all qualified applicants are considered for employment regardless of age ethnicity marital status citizenship race religion political affiliation gender sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: Experience:

Staff IC

About GlobalFoundries

Your Job

Architectural Leadership:Define and own the global DFT architecture including Hierarchical Scan Compressed ATPG Memory BIST/Repair (BISR) Logic BIST and IEEE 1687 (IJTAG) networks for multi-die orchiplet-based designs.

Test Strategy Optimization:Develop advanced strategies for defect-oriented testing (Cell-aware Slack-aware) andoptimizepattern volumes to balance aggressive coverage targets with tester memory constraints.

Cross-Functional Integration:Lead the integration of DFT requirements into RTL Synthesis and Physical Design (STA/PD) flows. Drive Design for Manufacturability (DFM) initiatives to improve yield.

Silicon Bring-up & Debug:Spearhead post-silicon validation and silicon bring-up. Own the root-cause analysis of complex test failures and provide expert-level debugging of ATE/System-level failures.

Methodology & Automation:Architect andmaintainscalable high-performance DFT flows using TCL Python or Perl. Evaluate and benchmark emerging EDA tool features to stay ahead of technology nodes (5nm/3nm and beyond).

Mentorship & Influence:Provide technical mentorship to junior and senior engineers. Act as a consultant for verification and backend teams to resolve bottleneck timing or routing issues caused by DFT structures.

Technical Documentation:Author comprehensive DFT specifications and strategy documents that serve as the Gold Standard for current and future project iterations.

Other Responsibilities

Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Securityrequirementsand programs.

Required Qualifications

Education:Bachelors Masters in Electrical Engineering Computer Engineering or related fields.

Experience:8 yearsof hands-on DFT experience with a proventrack recordof successfully taping out multiple complex SoCs.

Tool Mastery:Expert-levelproficiencywith industry-standard EDA suites (e.g.SynopsysTestMAX/DFTMAX Cadence Modus or Siemens/MentorTessent).

Advanced Logic Knowledge:Deep understanding of scan compression architectures (EDT/Adaptive Scan) hierarchical DFT and mixed-signal test integration.

Scripting:Advancedproficiencyin TCL and Python/Perl for developing custom CAD attributes and automating complex EDA flows.

Problem Solving:Demonstratedability to solve showstopper timing closure issues related to DFT or complex ATPG coverage gaps.

Preferred Qualifications

Specialized Flows:Experience withAutomotive ASIL-Dfunctional safety requirements including In-System Test (IST) and periodic logic/memory monitoring.