ASICVLSI Design Engineer

Job Title: ASIC/VLSI Design Engineer
Work Location: Austin TX
Work Type: Onsite
Duration: Fulltime
Visa: Any Visa

NOTE: Minimum 5 years of experience as ASIC/FPGA designer with Strong Verilog/System-Verilog experience

Job Summary:
Our client is a Series-D semiconductor innovator specializing in programmable coherent DSP (digital signal processing) solutions for cloud and AI infrastructure a foundational technology that enables faster and more efficient transmission within and between AI data centers.
The firm is empowering the future of AI infrastructure and cloud connectivity with DSP innovations.
The firm recently came out of stealth with $180MM funding and is backed by storied venture investors including Kleiner Perkins Spark Capital Mayfield and Fidelity Investments.
About The PositionWe are looking for talented and experienced VLSI Design Engineers/Micro-architects.
As an VLSI Design Engineer/Micro-architect youll have the opportunity to design highly sophisticated innovative new cutting edge communication systems from scratch.
Youll be joining a company at the forefront of transformative coherent DSP technology working with industry veterans and top-tier investor backing.
This is an opportunity to make a significant impact in powering the next generation of AI connectivity.

Responsibilities
Work closely with Algorithm and Architecture teams - Understand and translate high-level algorithmic requirements into efficient hardware implementations.
Learn and analyze relevant protocols and standards - Interpret protocol specifications (e.g.
Ethernet etc.) and apply them accurately in design.

Participate in all design stages:
Micro-architecture definition
RTL coding (using Verilog/SystemVerilog)
Synthesis-friendly coding and timing-aware design

Collaborate cross-functionally:
Verification team: For testbench development debug support and functional coverage closure.
DFT team: Ensure design is scan-insertable supports ATPG BIST etc.
Backend/Physical design team: For floorplanning timing closure and routing feedback.
Participate in Design Reviews - Present and defend design decisions in peer and formal reviews.
Perform Synthesis and Timing Analysis - Generate synthesis constraints (SDC) run synthesis and analyze timing reports.
Debug and Fix Functional/Timing Issues - Collaborate in post-silicon or pre-silicon debug; use waveforms assertions and logic analyzers.
Optimize for Area Power and Performance (PPA) - Identify bottlenecks and opportunities for improvement within RTL.
Documentation - Maintain clear design documentation for reusability and reference (e.g. micro-architecture specs interface docs).
Contribute to IP/SoC Integration - Work on integrating design blocks into larger systems and handling system-level interfaces.
Participate in Silicon Bring-up and Validation (optional but valuable) - Support bring-up of first silicon and assist with post-silicon validation if applicable.
Keep up-to-date with Industry Trends and Tools - Learn new EDA tools languages and methodologies (e.g. CDC Linting Formal Verification).

Requirements:
5 years of experience as ASIC/VLSI designer
RTL coding proficiency in Verilog/SystemVerilog
Good familiarity with modern ASIC design flow and methodologies including most of these domains: High speed design Low power design techniques integration of 3rd party IPs Lint CDC RDC SVA Synthesis SDC

Nice to have
DFT knowledge - Need to ensure designs support scan insertion ATPG BIST
Experience with Optical Communication systems
Design DSP of oriented blocks
Ethernet (100G and above)
Scripting experience using several of the following: Python Perl TCL
Work on IP/SoC integration and system-level interfaces
Self starter - ability to work with minimal supervision
Strong team player solid interpersonal skills
Entrepreneurial can-do attitude self-motivated able to work independently
BS/MS in Electrical Engineering / Computer Engineering from lead universities


Vishal (Victor) Verma Assistant Manager

NS IT Solutions

Required Skills:

RDCASICETHERNETVLSIATPGPERLPYTHON