Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks. Responsibilities include transistor level block level and module level circuit architecture design simulation optimization layout supervision layout verification preparation of test plan for the test group product characterization reliability and yield assessment and modeling simulation to bench and bench to test correlation bench evaluation both at silicon level and at applications level and documentation. Job responsibilities require ability to communicate at all levels and with cross functional groups. Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation must be a team player be adaptable and be open to feedback.
Qualifications :
- Must have hands-on design and development experience in analog and mixed-signal integrated circuits
- Must have experience in at least one preferably multiple area of full CMOS circuit design and development:
- Amplifiers operational instrumentation wide-bandwidth amplifiers etc.
- PMIC Linear and switched regulators Low-drop out regulators etc.
- Data converters ADC DAC Flash and SAR type
- Must have experience in 40nm and below CMOS technology
- Must have a demonstrable track record of successful design releases and mass production
- Must have thorough knowledge of industry standard EDA tools (Cadence Mentor Siemens Ansys etc.)
- Experience with analog high performance layout techniques - mismatch reduction gradient suppression parasitic effects minimization
- Experience with floor planning block level routing and top level chip routing
- Knowledge of high performance and deep CMOS analog reliability considerations such as EM-IR SOA and VDR and relevant mitigation techniques
- Functional knowledge of logic and digital circuits and understanding of basic digital design flow
- Experience working with distributed design teams a plus
- Must possess strong written and verbal communication skills
- BSEE with experience at a Technologist level
- MSEE with experience Technologist level
- PhD with experience Technologist level
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Compensation & Benefits Details
Notice To Candidates: Please be aware that WD and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment. Should you encounter any such requests please report it immediately to WD Ethics Helpline or email .
Remote Work :
No
Employment Type :
Full-time
Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks. Responsibilities include transistor level block level and module level circuit architecture design simulation optimization layout supervision layout verification preparation of test plan for the t...
Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks. Responsibilities include transistor level block level and module level circuit architecture design simulation optimization layout supervision layout verification preparation of test plan for the test group product characterization reliability and yield assessment and modeling simulation to bench and bench to test correlation bench evaluation both at silicon level and at applications level and documentation. Job responsibilities require ability to communicate at all levels and with cross functional groups. Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation must be a team player be adaptable and be open to feedback.
Qualifications :
- Must have hands-on design and development experience in analog and mixed-signal integrated circuits
- Must have experience in at least one preferably multiple area of full CMOS circuit design and development:
- Amplifiers operational instrumentation wide-bandwidth amplifiers etc.
- PMIC Linear and switched regulators Low-drop out regulators etc.
- Data converters ADC DAC Flash and SAR type
- Must have experience in 40nm and below CMOS technology
- Must have a demonstrable track record of successful design releases and mass production
- Must have thorough knowledge of industry standard EDA tools (Cadence Mentor Siemens Ansys etc.)
- Experience with analog high performance layout techniques - mismatch reduction gradient suppression parasitic effects minimization
- Experience with floor planning block level routing and top level chip routing
- Knowledge of high performance and deep CMOS analog reliability considerations such as EM-IR SOA and VDR and relevant mitigation techniques
- Functional knowledge of logic and digital circuits and understanding of basic digital design flow
- Experience working with distributed design teams a plus
- Must possess strong written and verbal communication skills
- BSEE with experience at a Technologist level
- MSEE with experience Technologist level
- PhD with experience Technologist level
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Compensation & Benefits Details
Notice To Candidates: Please be aware that WD and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment. Should you encounter any such requests please report it immediately to WD Ethics Helpline or email .
Remote Work :
No
Employment Type :
Full-time
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