Systems Design Engineer (Emulation and Prototyping)  Intermediate

Santa Clara County, CA - USA

Monthly Salary: Not Disclosed

Posted on: 5 hours ago

Vacancies: 1 Vacancy

Job Summary

Overview:

TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.

Job Title: Systems Design Engineer (Emulation and Prototyping) - Intermediate

Work Location: San Jose CA 95054

Duration: 12 Months

Work Type: Temporary Assignment

Job Type: Hybrid

Job Description:

JOB DUTIES:

In this position the engineer will have the following key responsibilities:
Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues.
Compile emulation model.
Debugging issues found during the process bring-up validation and production phases of SOC programs.
Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance.
Partition large SoC RTL for multi FPGA platforms; develop and maintain HAPS/FPGA build infrastructure including scripts flows and makefiles.
Integrate custom transactors high speed interfaces and debug instrumentation.
Work with various pre-silicon tools and concepts such as emulation FPGA software models N-1 silicon usage etc. including pre-to-post-silicon initiatives
We are looking for someone with close to 3-5 years of experience in hardware design.

Must have skills:

FPGA Design Experience
RTL Design using Verilog/System Verilog
Exposure to any Emulation or Prototyping Platform (HAPS/Zebu Protium/Palladium

EXPERIENCE AND EDUCATION:

3-4 years of experience on emulation based functional and performance verification for multimillion gate SoC designs. Should have strong exposure to RTL coding and SOC bring-up.
Hands on experience with Synopsys HAPS Protium Palladium or other FPGA/emulation platforms.
Experience with SoC buses and protocols: AXI ACE APB PCIe DDR Ethernet SerDes based links etc. Strong RTL design background using SystemVerilog/Verilog.
Good debugging skills experience of working with various debugging tools on RTL like Verdi fsdb analysis.
Familiarity with ASIC design flows including emulation verification and bring up.
Expertise in scripting/automation: Python Perl Tcl Make/CMake Shell.

TekWissen Group is an equal opportunity employer supporting workforce diversity.

Overview: TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors...