Sr Principal Design Engineer
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Job Location:
Monthly Salary:
Posted on:
15 hours ago
Vacancies:
1 Vacancy
Job Summary
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Experience: 10- 15 years
Location - Bangalore/Pune/
Responsibilities:
Complete DFT ownership of projects including:
Test architecture definition.
Identifying and implementing RTL changes for DFT.
Performing scan insertion LEC checks low power CLP checks.
Developing timing constraints for test mode timing closure.
Scan and ATPG for different fault models.
Boundary scan ACJTAG IEEE 1500 implementation and verification.
IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
Running zero delay and timing simulations and debugging on all the above aspects.
Supporting post silicon bring up.
Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
Experience working on very high speed and low power designs.
Were doing work that matters. Help us solve what others cant.
Required Experience:
Staff IC
Key Skills
- Design
- Academics
- AutoCAD 3D
- Cafe
- Fabrication
- Java
About Company
Do you want to shape the future of technology? Cadence is leading the charge to solve some of technology’s toughest challenges. We work with the world’s most innovative companies, across a growing range of industries. Major trends that you hear about everyday – like artificial intell ... View more
