Analog Layout Mid Senior Engineer

Senior Analog Layout Engineer (6-8 Years of Expereince) Bengaluru

About the Role

The Senior Analog Layout Engineer owns complex AMS and custom digital block layouts within the SoC flow delivering PV clean production ready designs in advanced CMOS. You will translate schematics into robust layouts independently execute block and IP level floorplanning routing and DRC/LVS/PEX closure while optimizing matching parasitics signal integrity area and reliability. Working closely with the Lead Layout Engineer and analog design team you will support planning provide effort estimates perform peer reviews and mentor junior engineers without formal people management responsibility.

• Implement full-custom layout for analog and mixed-signal IPs (e.g. amplifiers data converters SERDES RF/PM blocks bias/reference circuits) using Cadence Virtuoso in advanced CMOS nodes.

• Perform robust floorplanning of blocks and IPs considering matching routing symmetry parasitic minimization isolation shielding power distribution ESD and IO constraints and overall area efficiency.

• Ensure layouts are DRC- LVS- and ERC-clean working with Mentor Calibre (or equivalent) to debug and close all physical verification issues in a timely manner.

• Generate and validate extracted views (PEX) and support the design team during post-layout simulation and correlation iterating the layout as needed to meet performance targets.

• Collaborate closely with analog designers to understand schematics constraints and trade-offs and propose layout solutions that balance performance area EM/IR and schedule.

• Contribute to pad-ring and chip-top level integration by implementing or integrating pad cells analog IPs and digital GDS ensuring clean hierarchy correct connectivity and adherence to ESD and floorplan guidelines.

• Apply design-for-manufacturability (DFM) and reliability best practices (fill guard rings dummy devices antenna rules EM constraints etc.) to ensure robust silicon.

• Perform peer reviews of layouts done by junior engineers provide constructive feedback and support them in debugging DRC/LVS/PEX and layout-quality issues.

• Work with the Lead Layout Engineer to provide effort estimates identify layout risks early and help track progress against project milestones.

• Contribute to internal layout guidelines checklists and best practices to continuously improve team productivity and layout quality.

• Strong expertise in full-custom analog/AMS layout using Cadence Virtuoso (Layout XL) including device-level and block-level implementation in advanced technology nodes.

• Hands-on experience with physical verification tools preferably Mentor Calibre (DRC LVS ERC PEX) and solid understanding of the associated rule decks and debugging flows.

• Proven experience in FinFET and/or advanced Planar Si CMOS technologies; understanding of device structures design rules and layout constraints specific to these processes.

• Solid understanding of layout techniques for matching low-noise precision high-speed and high-voltage circuits including common-centroid interdigitation shielding guard rings and isolation.

• Practical experience in layout of at least one of the following domains:

  • High-speed SERDES or high-speed IOs

  • RF front-end or RF building blocks

  • Power management (LDOs DC-DC charge pumps drivers)
    with willingness to ramp up across other domains as needed.

• Working knowledge of pad-ring and chip-top level concepts integration of analog IPs and digital GDS power domains ESD structures and seal-ring implementation.

• Good understanding of DFM principles and reliability considerations (density/fill rules stress effects via redundancy EM/IR latch-up and ESD awareness at layout level).

• Ability to systematically troubleshoot layout-related issues and PV violations and to drive them to closure with minimal supervision.

• Strong collaboration skills with designers and verification teams and clear communication of layout constraints risks and trade-offs.

• B.E./ or M.E./ in Electronics Electrical VLSI or a closely related discipline from a reputed institution.

• 6 8 years of relevant industry experience in analog/AMS layout for SoCs or complex mixed-signal ASICs.
  
  

• Exposure to SiGe or GaN technologies for RF or power applications is a plus.
• Experience contributing to layout flows automation scripts or PCells is advantageous.
• Prior experience informally mentoring junior layout engineers or leading small block-level efforts will be considered a strong plus.