Analog Layout Engineer
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Job Location:
Santa Clara County, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
Job Description:
Senior layout designer will be responsible for layout of high-performance analog cores such as analog-to-digital converters digital-to-analog converters PLL transceivers etc.
Responsibilities include leading IC layout of cutting-edge high-performance high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm 5nm 7nm 16nm following best practices from the industry.
Senior layout designer will be responsible for layout of high-performance analog cores such as analog-to-digital converters digital-to-analog converters PLL transceivers etc.
Responsibilities include leading IC layout of cutting-edge high-performance high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm 5nm 7nm 16nm following best practices from the industry.
Qualifications
Thorough knowledge of industry standard EDA tools from Cadence Mentor and Synopsys.
Must be able to set up Mentorenvironments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters references digital to analog converters PLL etc. desired.
Experience with floor planning block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout shielding use of dummy devices thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10 years experience in high performance analog layout in advanced CMOS process.
Thorough knowledge of industry standard EDA tools from Cadence Mentor and Synopsys.
Must be able to set up Mentorenvironments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters references digital to analog converters PLL etc. desired.
Experience with floor planning block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout shielding use of dummy devices thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10 years experience in high performance analog layout in advanced CMOS process.
Key Responsibilities:
Experience in IC layout of cutting-edge high-performance high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm 5nm
Key Skills
- Design Engineering
- Design
- Engineering
- Design Management
- Control System
