Physical Design Power GridIREM Engineer

Please Note:

1. If you are a first time user please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account please Sign-In before you apply.

Job Description:

An ASIC IR/EM (Internal Resistance / Electromigration) Engineer focuses on the physical reliability and power integrity of advanced integrated circuits. This role typically owns flow/methodology and works closely with the Physical Design to ensure that high performance chips do not fail due to excessive voltage drop or wire burnout.

Key Responsibilities:

• Lead and execute power/EMIR methodology implementation and signoff

• Design and optimize the power straps / mesh to balance IR drop performance with routing congestion and area

• Work closely with physical design implementationto ensure EMIR convergence at all stages

• Apply PPA optimization techniques (performance/timing closure power reduction area efficiency) across block and full-chip hierarchies

• Collaborate with front-end design architecture and CAD/EDA tool teams to ensure physical design constraints timing budgets power budgets and DFT criteria are met

• Develop and enhance EMIR flows methodologies scripts and automation frameworks (TCL Python Perl) to accelerate turnaround improve QoR and reduce manual intervention

• Collaborate with packaging teams to ensure designs are run with CPM models

• Debug design issues and work with CAD tool vendors to drive tool enhancements or implement workarounds

• Mentor junior engineers contribute to design reviews document flows and promote continuous process improvement

Minimum experience:

• Bachelors degree in Electrical Engineering Computer Engineering or a related technical field and 8 years or Masters degree in Electrical Engineering Computer Engineering or a related technical fieldand 6 years of hands-on experience in IR /EM analysismethodology or physical design for multi-voltage and large SoCs

• Good understandingof UPF based power intent power grid architecture and EMIR analysis using the industrys most advanced toolsets (RedHawk Voltus etc.)

• Advanced scripting abilities (Tcl Python Perl) for architecting resilient automated flows

• Proven impact delivering robust solutions on leading-edge FinFET nodes across the complete RTL-to-GDSII lifecycle

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $120000- $192000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP) company paid holidays paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race color creed religion sex sexual orientation national origin citizenship disability status medical condition pregnancy protected veteran status or any other characteristic protected by federal state or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA please be sure to fill out a home address as this will be used for future correspondence.