SOC DFT Engineer Intern Summer 2026

NXP Semiconductors

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profile Job Location:

Austin, TX - USA

profile Monthly Salary: Not Disclosed
Posted on: Yesterday
Vacancies: 1 Vacancy

Job Summary

Job Title:DFT Intern

Location:Austin TX (On-site/Hybrid)
Department:Digital Design DFT
Reports To:DFT Engineer / Manager

About the Role:

We are seeking a highly motivated and detail-orientedDesign for Test (DFT) Internto join our Digital Design team. As a DFT Intern you will work closely with experienced engineers to support the development and implementation of DFT methodologies for cutting-edge SoC designs. This internship offers hands-on experience in scan insertion ATPG MBIST and other test-related flows in a real-world semiconductor environment.

Key Responsibilities:

  • Assist in the implementation of DFT techniques such as scan insertion boundary scan and memory BIST.
  • Support ATPG pattern generation and validation using industry-standard tools.
  • Help with test coverage analysis and debug of test patterns.
  • Collaborate with RTL designers and verification teams to ensure testability requirements are met.
  • Contribute to automation of DFT flows using scripting languages (e.g. Python Perl TCL).
  • Document DFT methodologies test plans and results.

Qualifications:

  • Currently pursuing aBachelors or Masters degreein Electrical Engineering Computer Engineering or a related field.
  • Strong understanding of digital logic design and VLSI fundamentals.
  • Familiarity with Verilog/VHDL and scripting languages (Python Perl or TCL).
  • Exposure to DFT concepts such as scan chains ATPG and BIST is a plus.
  • Experience with EDA tools from Synopsys Cadence or Mentor Graphics is desirable.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and teamwork abilities.

Preferred Skills (Nice to Have):

  • Coursework or project experience in DFT or digital IC design.
  • Knowledge of STA synthesis and RTL verification.
  • Familiarity with Linux/Unix environments.

What Youll Gain:

  • Hands-on experience with industry-standard DFT tools and flows.
  • Mentorship from experienced engineers in a collaborative environment.
  • Exposure to the full ASIC design and test cycle.
  • Opportunity to contribute to real silicon projects.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age color national origin race religion creed gender sex sexual orientation gender identity and/or expression marital status status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal state or local addition NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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Intern

Job Title:DFT InternLocation:Austin TX (On-site/Hybrid)Department:Digital Design DFTReports To:DFT Engineer / ManagerAbout the Role:We are seeking a highly motivated and detail-orientedDesign for Test (DFT) Internto join our Digital Design team. As a DFT Intern you will work closely with experience...
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