Analog Layout Manager MCU

NXPs Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXPs advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence enabling applications across the autonomous home industrial automation and personal electronics

NXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXPs intelligent AI at the Edge. This team will includea widerange of engineering talent from analog to SOC digital design. Full product development local willproductworld class products at a world class pace.

This team will include all key engineering disciplines in Design Architecture VerificationDfTand Physical Design to produce high performance and quality products.

Working inafast-pacedconsumerenvironment we are looking for an outstanding manager to lead our Analog Layout team will include support for MCU and for analog custom products being designed both in Catania but also globally.

The role will also involve frequent communication with key customers for detailed reviews.

YourResponsibilities

• Lead a team of analog layout engineers responsible for the physical design of analog blocks and systems

• Responsible for layout of Analog and RF components inMCUNFC UWB and BT/BLE products

• Workacrossmultiple processnodesandfoundries(140nm to 16 nm CMOS BCD FD-SOIFinFET )

• Develop theexpertiseof the team and drive innovation

• Provideaccurateestimateson areaperformanceand timeline

• Drive the team to meet aggressive schedules without sacrificing quality

• Work closely with analog design engineers to ensure seamless integration of layout and design

• Ensure layouts meet performance power and area requirements

• Develop andmaintainlayout scripts and automation tools

• Collaborate with cross-functional teams including digital layoutdesignand verification

• Perform layout verification (DRC LVS )and sign-off

• Deliver physical models (LEF Libs) to subsystem and IC teams for integration

YourProfile

• MastersDegree in Electronic/Electrical Engineering

• 10years experiencein the layout of analog blocks and systems

• Experience with leading a global team of engineers

• Proventrack recordin delivering working silicon for high volume products

• Solid fundamentals of transistor level integrated circuits and device physics.

• Knowledge of layout matching andparasitics latch-up ESD etc.

• Rigorous and methodical with good analytical skills for debugging issues in design and on silicon

• Proficiencyin analog layout tools such as Cadence Virtuoso SiemensCalibre..

• Knowledge of ESD/Latch up fundamentals

• Experience with signal chain and power design layouts