As an HBM Build Engineer at Micron Technology you will build simulate and analyze digital and analog circuits used to develop advanced DRAM and memory solutions. You will drive circuit design floorplanning parasitic modeling simulation silicon validation and tapeout revisions to ensure efficient power performance reliability and manufacturability. This role collaborates closely with Product Engineering Test Probe Process Integration Assembly Marketing CAD and other partners to deliver highquality products on time and at competitive cost. You will also contribute to design documentation critical reviews mentorship recruiting and project management activities supporting the full lifecycle of memory product development.

Responsibilities

• Design and optimize digital and analog DRAM circuitsincluding memory core circuits sense margins array timings and diesize efficiencybased on device specifications.

• Create and refine circuit floorplans to optimize placement routing parasitic behavior signal integrity and power delivery.

• Perform DRAM circuit verification using SPICE and Verilog analyzing power performance reliability and layout parasitics to ensure accurate circuit operation.

• Support DRAM silicon validation debug and correlation activities identifying schematic edits and driving reticle experiments and necessary tapeout revisions.

• Prepare detailed design documentation contribute to critical design reviews share best-known practices and participate in team technical forums.

• Collaborate with Product Engineering Test Probe Process Integration Assembly CAD and Marketing to support manufacturability qualification and product success.

• Manage project activities including resource allocation issue resolution schedule tracking and preparing status reports for management.

• Mentor engineers support recruiting and interviewing and lead design reviews to ensure project alignment and highquality design decisions.

Qualifications

• BS with 8 years or MS with 5 years of experience in circuit design VLSI or related technical fields.

• Coursework in CMOS circuit design VLSI and analog circuit design.

• Proficiency in Cadence Virtuoso and experience simulating with HSPICE and Verilog.

• Strong understanding of physical layout circuit floorplanning and device reliability.

• Excellent analytical problemsolving and debugging skills.

Preferred Qualifications

• Experience in DRAM HBM or other memory circuit design and validation workflows.

• Experience supporting reticle experiments silicon correlation and tapeout revision cycles.

• Proven ability to mentor engineers contribute to build reviews and support multi-functional collaboration.