The job opening is for a full-time Research Staff Member in the Design Group in Western Digitals research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digitals strategic radiation hardened memory technology.
The responsibilities for the role will include:
- Developing high density memory chip custom layout
- Including shared operational circuitry along with at pitch line drivers
- All phases of chip design layout to be included: From architecture definition density and performance optimization final verification up to and including tape out
- Running and Debugging Physical Verification flows including DRC LVS ERC and Antenna Checks
- Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications
- Comprehend and address reliability engineering issues such as electromigration IR Drop and Design For Manufacturing robustness
- Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry)
- Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WDs Fabrication Line
- Development of EDA Tool Design Rules for WDs Memory Array Layers
- Defining and executing the split-fab tape out flow
Qualifications :
Minimum of a Bachelors degree in Electrical Engineering Physics or closely related field with 8 years of professional experience or a Ph.D. with 3 years is required.
The prior track record of a viable candidate must show:
- Previous design layout tape out and validation of high density memory chip designs
- Capability to develop design layout schedules that meet chip functional requirements and timelines
- Proficiency in Cadence Virtuoso (VXL) Mentor Graphics Calibre or Synopsys IC Validator
- Capability to work closely with circuit designers to iterate on schematics and with process engineers to understand fabrication constraints
- Deep understanding of CMOS fabrication processes Phase-Shift Mask Development and Multi-Patterning Techniques
The following skills and experiences are highly desired
- Experience developing memory cell models for inclusion in simulation tool environment such as Verilog-A
- Experience with emerging memories such as MRAM ReRAM or PCM
- Experience developing Radiation Tolerant Layouts
- Track record of publications and patents related to memory design layout
Additional Information :
Western Digital is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race color ancestry religion (including religious dress and grooming standards) sex (including pregnancy childbirth or related medical conditions breastfeeding or related medical conditions) gender (including a persons gender identity gender expression and gender-related appearance and behavior whether or not stereotypically associated with the persons assigned sex at birth) age national origin sexual orientation medical condition marital status (including domestic partnership status) physical disability mental disability medical condition genetic information protected medical and family care leave Civil Air Patrol status military and veteran status or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the Know Your Rights: Workplace Discrimination is Illegal poster. Our pay transparency policy is available here.
Western Digital thrives on the power and potential of diversity. As a global company we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees our company our customers and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging respect and contribution.
Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation your email please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
Based on our experience we anticipate that the application deadline will be 01/14/2025 (3 months from posting) although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline we will update this posting with a new anticipated application deadline.
Compensation & Benefits Details
Notice To Candidates: Please be aware that Western Digital and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment. Should you encounter any such requests please report it immediately to Western Digital Ethics Helpline or email .
Remote Work :
No
Employment Type :
Full-time
The job opening is for a full-time Research Staff Member in the Design Group in Western Digitals research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digitals strategic radiation hardened memory technology. The responsib...
The job opening is for a full-time Research Staff Member in the Design Group in Western Digitals research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digitals strategic radiation hardened memory technology.
The responsibilities for the role will include:
- Developing high density memory chip custom layout
- Including shared operational circuitry along with at pitch line drivers
- All phases of chip design layout to be included: From architecture definition density and performance optimization final verification up to and including tape out
- Running and Debugging Physical Verification flows including DRC LVS ERC and Antenna Checks
- Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications
- Comprehend and address reliability engineering issues such as electromigration IR Drop and Design For Manufacturing robustness
- Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry)
- Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WDs Fabrication Line
- Development of EDA Tool Design Rules for WDs Memory Array Layers
- Defining and executing the split-fab tape out flow
Qualifications :
Minimum of a Bachelors degree in Electrical Engineering Physics or closely related field with 8 years of professional experience or a Ph.D. with 3 years is required.
The prior track record of a viable candidate must show:
- Previous design layout tape out and validation of high density memory chip designs
- Capability to develop design layout schedules that meet chip functional requirements and timelines
- Proficiency in Cadence Virtuoso (VXL) Mentor Graphics Calibre or Synopsys IC Validator
- Capability to work closely with circuit designers to iterate on schematics and with process engineers to understand fabrication constraints
- Deep understanding of CMOS fabrication processes Phase-Shift Mask Development and Multi-Patterning Techniques
The following skills and experiences are highly desired
- Experience developing memory cell models for inclusion in simulation tool environment such as Verilog-A
- Experience with emerging memories such as MRAM ReRAM or PCM
- Experience developing Radiation Tolerant Layouts
- Track record of publications and patents related to memory design layout
Additional Information :
Western Digital is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race color ancestry religion (including religious dress and grooming standards) sex (including pregnancy childbirth or related medical conditions breastfeeding or related medical conditions) gender (including a persons gender identity gender expression and gender-related appearance and behavior whether or not stereotypically associated with the persons assigned sex at birth) age national origin sexual orientation medical condition marital status (including domestic partnership status) physical disability mental disability medical condition genetic information protected medical and family care leave Civil Air Patrol status military and veteran status or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the Know Your Rights: Workplace Discrimination is Illegal poster. Our pay transparency policy is available here.
Western Digital thrives on the power and potential of diversity. As a global company we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees our company our customers and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging respect and contribution.
Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation your email please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
Based on our experience we anticipate that the application deadline will be 01/14/2025 (3 months from posting) although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline we will update this posting with a new anticipated application deadline.
Compensation & Benefits Details
Notice To Candidates: Please be aware that Western Digital and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment. Should you encounter any such requests please report it immediately to Western Digital Ethics Helpline or email .
Remote Work :
No
Employment Type :
Full-time
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