High-Speed CMOS DACADCPLL Analog Design Engineer
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Job Location:
Los Angeles, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
17 hours ago
Vacancies:
1 Vacancy
Job Summary
High-Speed CMOS DAC/ADC/PLL Analog Design Engineer
Locations: Irvine CA San Jose CA or possibly remote
US Citizen or US Permanent Resident preferred
Full-time Employee Bonus Benefits 401k Stock Options
Duties & Responsibilities:
Clock generation and distribution (VCOs PLL clock distribution etc)
Design of custom passive components from concept to silicon implementation
Fundamental analog blocks (bandgap references LDOs temp sensors etc)
High-speed analog circuit design such as high-speed broadband amplifiers (VGA CTLE DRV etc.)
New techniques for the development of next generation optical transceiver
Silicon bring-up debug and support
Supervise analog layouts within advanced process nodes
System verification and circuit design spec creation
Team communication and documentation
Required Experience:
BSEE/MSEE and/or PhD (preferred) in Electrical Engineering or related fields with 5 years of experience
Experience with analog design and verification tools (Virtuoso Spectre ADE and post layout extraction tools) is a must
Experience with electromagnetic simulation tools (EMX Momentum HFSS or other)
Experienced in lab chip bring-up and debugging efforts is a plus
Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus
Knowledge of the fundamentals on electromagnetism lump models and high frequency design
Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification clock generation and distribution and/or fundamental analog blocks
Strong communication and documentation skills
Locations: Irvine CA San Jose CA or possibly remote
US Citizen or US Permanent Resident preferred
Full-time Employee Bonus Benefits 401k Stock Options
Duties & Responsibilities:
Clock generation and distribution (VCOs PLL clock distribution etc)
Design of custom passive components from concept to silicon implementation
Fundamental analog blocks (bandgap references LDOs temp sensors etc)
High-speed analog circuit design such as high-speed broadband amplifiers (VGA CTLE DRV etc.)
New techniques for the development of next generation optical transceiver
Silicon bring-up debug and support
Supervise analog layouts within advanced process nodes
System verification and circuit design spec creation
Team communication and documentation
Required Experience:
BSEE/MSEE and/or PhD (preferred) in Electrical Engineering or related fields with 5 years of experience
Experience with analog design and verification tools (Virtuoso Spectre ADE and post layout extraction tools) is a must
Experience with electromagnetic simulation tools (EMX Momentum HFSS or other)
Experienced in lab chip bring-up and debugging efforts is a plus
Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus
Knowledge of the fundamentals on electromagnetism lump models and high frequency design
Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification clock generation and distribution and/or fundamental analog blocks
Strong communication and documentation skills
Required Experience:
IC
Key Skills
- Children Activity
- Generator
- Geotechnical Engineering
- Advocacy
- Health Club
- Adobe Photoshop
