Senior SoC Design Verification Engineer (remote)
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Job Location:
Andover, KS - USA
Monthly Salary:
Not Disclosed
Posted on:
11 hours ago
Vacancies:
1 Vacancy
Job Summary
Senior Design Verification Engineer
Remote / work from any US location
US Citizen or US Permanent Resident
Full-time/employee Bonus Benefits 401k Stock Options
Responsibilities:
Contribute to the development of novel methodologies and verification techniques
Create and maintain testbenches test cases and test vectors
Develop and execute verification plans for digital designs using SystemVerilog and UVM
Document plans environments test cases and all results for a comprehensive record of all verification strategies
Implement coverage tracking and metrics
Lead technical projects and mentorship of junior team members.
Run simulations to verify design against specifications. Analyze results identify issues and debug designs
Requirements:
7 years of hands-on experience in SoC verification using UVM
Bachelors degree in Electrical Engineering Computer Engineering or related field
Experience in Gate-Level Simulation (GLS) setup and process corner failure analysis
Experience using Cadence verification tools such as VCS Verdi and Spyglass
Experience writing and debugging RTL using SystemVerilog
Familiarity with digital design concepts and ASIC development flow
Programming experience using C C and/or Python/Perl
Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex multidisciplinary tasks and projects
Ability to work collaboratively across teams and communicate effectively
Attention to detail and remarkable eye for accuracy
Strong analytical and problem-solving skills
Willingness to learn and develop new skills
Preferred Skills:
Experience verifying high-speed interfaces such as PCIe and DDR
Experience verifying RISC-V based systems
Experience with emulation or FPGA prototyping
Experience with Formal Verification methodologies
Experience with the CHISEL Hardware Description Language (HDL)
Experience with version control systems (e.g. Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
DESIGN VERIFICATION GROUP on LinkedIn: #SoC #UVM
Remote / work from any US location
US Citizen or US Permanent Resident
Full-time/employee Bonus Benefits 401k Stock Options
Responsibilities:
Contribute to the development of novel methodologies and verification techniques
Create and maintain testbenches test cases and test vectors
Develop and execute verification plans for digital designs using SystemVerilog and UVM
Document plans environments test cases and all results for a comprehensive record of all verification strategies
Implement coverage tracking and metrics
Lead technical projects and mentorship of junior team members.
Run simulations to verify design against specifications. Analyze results identify issues and debug designs
Requirements:
7 years of hands-on experience in SoC verification using UVM
Bachelors degree in Electrical Engineering Computer Engineering or related field
Experience in Gate-Level Simulation (GLS) setup and process corner failure analysis
Experience using Cadence verification tools such as VCS Verdi and Spyglass
Experience writing and debugging RTL using SystemVerilog
Familiarity with digital design concepts and ASIC development flow
Programming experience using C C and/or Python/Perl
Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex multidisciplinary tasks and projects
Ability to work collaboratively across teams and communicate effectively
Attention to detail and remarkable eye for accuracy
Strong analytical and problem-solving skills
Willingness to learn and develop new skills
Preferred Skills:
Experience verifying high-speed interfaces such as PCIe and DDR
Experience verifying RISC-V based systems
Experience with emulation or FPGA prototyping
Experience with Formal Verification methodologies
Experience with the CHISEL Hardware Description Language (HDL)
Experience with version control systems (e.g. Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
DESIGN VERIFICATION GROUP on LinkedIn: #SoC #UVM
Required Experience:
Senior IC
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
