System on Chip Architect

At Google DeepMind we value diversity of experience knowledge backgrounds and perspectives and harness these qualities to create extraordinary impact. We are committed to equal employment opportunity regardless of sex race religion or belief ethnic or national origin disability age citizenship marital domestic or civil partnership status sexual orientation gender identity pregnancy or related condition (including breastfeeding) or any other basis as protected by applicable law. If you have a disability or additional need that requires accommodation please do not hesitate to let us know.

Snapshot

At Google DeepMind weve built a unique culture and work environment where long-term ambitious research can flourish. We are seeking a highly motivated SoC Architect to join our team and contribute to the development of groundbreaking silicon for machine learning acceleration.

About us

Artificial Intelligence could be one of humanitys most useful inventions. At Google DeepMind were a team of scientists engineers machine learning experts and more working together to advance the state of the art in artificial intelligence. We use our technologies for widespread public benefit and scientific discovery and collaborate with others on critical challenges ensuring safety and ethics are the highest priority.

About you

We seek out individuals who thrive in ambiguity and who are willing to help out with whatever moves silicon design and architecture forward. We regularly need to invent novel solutions to problems and often change course if our ideas dont work out so flexibility and adaptability to work on any project is a must.

The Role

We are seeking a talented and highly motivated SoC Architect to join our GenAI technical infrastructure research hardware team. You will be responsible for defining the top-level SoC architecture and chiplet strategy for our next-generation ML accelerators. This role requires deep expertise in SoC design chiplet integration and ML-specific hardware.

Responsibilities:

• Define and own the System-on-Chip (SoC) architecture for next-generation ML accelerators.
• Lead the architecture and design of the chip top-level managing interfaces clocking power and integration of all major IP blocks.
• Architect specific accelerator components and chiplets.
• Collaborate with micro-architecture and physical design teams to ensure a feasible and optimal design making trade-offs in performance power and area (PPA).
• Work with systems and software teams to ensure the SoC architecture meets product requirements.
• Participate in the system architecture definition and evaluation.

Minimum Qualifications:

• Bachelors degree in Electrical Engineering Computer Science or equivalent practical experience.
• 7 years of experience in SoC architecture or micro-architecture.
• Proven experience in chip top-level design and integration for complex ASICs.
• Hands-on knowledge of hardware building blocks for ML accelerators (matrix multiply units vector engines attention mechanisms).
• Experience in evaluating trade-offs such as speed performance power and area.

Preferred Qualifications:

• Masters or Ph.D. in a related field.
• Experience with chiplet-based designs and high-speed die-to-die interconnects (e.g. UCIe CXL).
• Knowledge of high-performance and low-power architectures for ML acceleration.
• Working knowledge of transformer-based large language models.
• Good understanding of the full ASIC design flow (RTL verification synthesis PD).