Digital Libraries Design Engineer – Characterization

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Job Description:

As a Design Engineer specializing in Libraries Cell (Standard Cells & IOs) you will be responsible for the characterization and delivery of
high-quality CMOS cell libraries for high-speed low-power and automotive applications across various foundry and process technologies.
Your role will involve:
Performing comprehensive characterization including NLDM and CCS Ibis models (cell & chip level)
Exposure to advanced characterization techniques such as AOCV and LVF modeling is a plus.
Writing and simulating behavioral Verilog models for digital Libraries cells.
Creating and validating EDA tool views for library integration.
Conducting library comparisons and benchmarking for power performance and area.
Releasing digital libraries with thorough quality checks and documentation.

Requirements/Qualifications:

Bachelors degree in Electronics/Electronics & Communication Engineering with a minimum of 4 years of experience in the
semiconductor industry; a Masters degree is a plus.
Proven hands-on experience in Digital libraries development and characterization.
Strong understanding of CMOS and FinFET technologies.
Experience with Verilog modeling is highly desirable.
Excellent debugging and problem-solving skills in cell design SPICE simulation and characterization.
Proficiency with EDA tools such as Cadence Virtuoso Calibre HSPICE and other industry-standard simulation and characterization
tools.
Programming skills in Perl TCL and Cadence SKILL are advantageous.

Travel Time:

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