Principal Hardware Engineer Technical LeadArchitect for Boardlevel system design for storage, custom ASIC

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Seeking a versatile self-motivated team-oriented board design engineer to develop high density high volume next generation products. Our products support a wide range of communicationinfrastructure applications including Fiber Channel (FC) NICs optical modules network security datacenter systems and cloudcomputing platforms. The candidate will collaborate closely with Marvell ASIC/hardware/software design teams lead technical discussions with customers and oversee design deliverables from Contract Manufacturers to ensure highquality execution. The candidate will also have a good debug skills and experience in using lab equipment. Expertise in design for optimum signal and power integrity as well as hands-on lab measurements experience is a must.

• Provide technical leadership and engineering support to strategic customers including creation and presentation of power point files for customer review and discussions
• Work directly with customers to address design challenges debug failures and ensure successful product integration.
• Architect and design highperformance boardlevel systems for storage network security and custom ASIC applications.
• Manage designs with JDM partners to provide design guidance support build readiness and ensure production quality.
• Define design and review schematics from internal hardware teams and JDM with emphasis on highspeed signal integrity power integrity and costoptimized designs for highvolume production.
• Review PCB layouts in collaboration with layout engineering teams.
• Work closely with the internal board development DVT and SI teams to make sure board issues are addressed resolved and closed
• Conduct design reviews with clear documentation and provide technical leadership throughout the product development cycle.
• Collaborate with crossfunctional teams to ensure product performance reliability and quality.
• Define document execute and report on boardlevel electrical tests.
• Facilitate technical discussions and drive resolution of complex engineering issues.

What Were Looking For

• Bachelors degree in Computer Science Electrical Engineering or a related field with 15 years of relevant industry experience OR a Masters degree with 10 years of experience.
• 12 years of experience in boardlevel hardware design and system architecture including fine pitch components and micro-vias.
• 5 years of experience working with ODM/JDM
• Proficiency with schematic capture tools (Cadence OrCAD Allegro HDL) and familiarity with Allegro PCB layout tools.
• Strong expertise in highspeed interfaces and protocols including PCIe Gen5 DDR4/5 Ethernet QSPI and USB etc.
• Demonstrated customerfacing experience with excellent verbal and written communication skills.
• Proven criticalthinking abilities strong problemsolving skills and a sense of ownership for team and project outcomes.
• Advanced lab skills with handson experience in hardware bringup systemlevel testing power supply design and troubleshooting.
• Experience working with PCIe Ethernet and OCP standards.
• Knowledge of highspeed SerDes technologies including 112G/224G.
• Familiarity with EMC/EMI compliance regulatory and safety standards and the ability to interpret test lab reports.
• Basic Linux proficiency for system test environment setup (highly preferred).
• Working knowledge of mechanical and thermal design principles including interpretation of 2D and 3D drawings.
• Experience with Agile PLM tools is considered a plus.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.