Tech Lead FPGA Senior Design Verification Engineer (SystemVerilog UVM)

Redmond, WA - USA

Monthly Salary: Not Disclosed

Posted on: 2 hours ago

Vacancies: 1 Vacancy

Job Summary

Tech Lead FPGA /Senior Design Verification Engineer (SystemVerilog / UVM)

Location: Redmond Seattle Washington

Experience: 8-15 and not more than 18 years

Onsite: YES @ customer location

Duration; Long Term

Visas: H1b/USC and GC

JD:

He should have some lead experience even hands on experience in also fine.

Design Verification expertise in System Verilog /UVM for Unit/Module level Verification

Should have Lead Design Verification Team ( Min 5 Members)

Strong background in developing UVM Testbenches from scratch

Experience in VIP Integration and Bring up

Porting Existing Verilog/VHDL environment to UVM based Environment

Experience in test planning Coverage Coding and Debugging

Deep Knowledge of AMBA Protocol is must

Tech Lead FPGA /Senior Design Verification Engineer (SystemVerilog / UVM) Location: Redmond Seattle Washington Experience: 8-15 and not more than 18 years Onsite: YES @ customer location Duration; Long Term Visas: H1b/USC and GC JD: He should have some lead experience even hands on experience ...