AnalogRF Design Engineer Intern Master's Degree

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Marvell is seeking an RF/Analog Design Intern to contribute to the development of high-speed transimpedance amplifiers (TIAs) and Drivers. These optical interface chips are tightly coupled with our high-performance equalizers. The results of our innovative designs have made our TIAs and Drivers best in class for AI and data center this role you will be responsible for:

• Active-circuit design.

• Design of leading edge transimpedance amplifiers using both SiGe BiCMOS and the most advanced CMOS FinFET technologies.

• Design of high-performance broadband analog circuits for optical front-end receivers.

• Design of various other analog circuits including linear regulators AGC loops current/voltage sensors bandgaps etc.

What Were Looking For

• Currently enrolled in an MSc. or PhD program in electrical engineering or a related field.

• Deep understanding of fundamentals including:

  • Detailed transistor level design.

  • Device physics.

  • Control/Feedback loop stability analysis.

• Solid experience in.

  • Using EDA CAD tools

  • Performing Analog Custom Layout

• Experience in measuring IC performance and debug of design to correlate simulations to measurements.

• Direct experience in one of the following areas is a plus:

• • High-speed broadband circuits.

  • Automatic gain-control loops.

  • High precision analog circuits including linear regulators current sensors bandgaps and DAC/ADC.

  • Continuous-time linear equalizers.

• Experience in using different technologies. (SiGe BiCMOS and FinFET CMOS are pluses)

• Ability to work in a team.

• Strong communication presentation and documentation skills.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.