Senior Principal Engineer, Physical Design

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

As a senior leader in the central physical design team you will:

• Shape the long-term vision for physical design capabilities and infrastructure in alignment with company-wide technology strategy

• Lead RTL-to-GDSII implementationfor multiple SoC programs overseeing synthesis floorplanning power grid design place and route clock tree synthesis timing closure power/signal integrity signoff and physical verification (DRC/LVS)

• Providestrategic leadership and technical directionto physical design teams ensuring successful and timely tapeouts of complex high-performance SoCs

• Mentor and develop engineering talent fostering a culture of innovation collaboration and continuous improvement

• Oversee team structure hiring performance management and career development to build and retain a high-performing physical design organization

• Drive cross-functional collaboration with design teams to influence design decisions and ensure successful project execution

• Navigate and resolve cross-functional conflicts effectively fostering alignment and maintaining momentum across diverse teams

• Drive thedevelopment and adoption of next-generation physical design methodologies flows and automation to improve productivity and design quality

What Were Looking For

• Bachelors degree in Computer Science Electrical Engineering or related fields and 15 years of related professional experience or Masters degree in Computer Science Electrical Engineering or related fields with 10-12 years of experience or PhD in Computer Science Electrical Engineering or related fields with 8-10 years of experience or equivalent professional experience in lieu of a formal degree

• 15 years of progressive experience in back-end physical design and verification including significant leadership roles

• Proven track record of leading and scaling physical design teams managing complex SoC projects and delivering high-quality tapeouts under aggressive schedules

• Deep expertise in hierarchical physical design strategies methodologies and advanced process node challenges

• In-depth understanding of current design technologies used in major foundries

• Strong understanding of ASIC design flow RTL integration synthesis and timing closure

• In-depth knowledge of modern EDA tools and flows

• Proficient in automation and scripting using Makefile Tcl Python or Perl to enhance design efficiency and flow robustness

• Strong communication and collaboration skills with the ability to influence cross-functional teams and executive stakeholders

• Experience in developing and deploying advanced physical design methodologies and flows

• Strong knowledge on static timing analysis (PrimeTime Tempus) EM/IR-Drop/crosstalk analysis (PTSI Voltus Redhawk PrimeRail) extraction (Quantus StarRC) formal or physical verification (Formality Verplex Calibre Hercules) a plus

• Familiarity with AI/ML-driven optimization in physical design tools is a plus

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.