ASIC Intern

ASIC Intern
Location: San Jose CA
Team: Hardware Engineering (ASIC)

About Etched

Etched is building the worlds first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs you can build products that would be impossible with GPUs like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers Etched is redefining the infrastructure layer for the fastest growing industry in history.

The role

We are looking for interns across RTL Design Design Verification or Physical Design to join our team.

As an RTL Intern at Etched you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures contribute to RTL block development and participate in the full design cyclefrom microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced high-autonomy environment.

As a Design Verification intern you will ensure the custom IPs powering our chips including systolic arrays DMA engines and NoCs are robust high-performance and silicon-ready. This role demands creativity deep technical ability and the drive to tackle complex verification challenges. You will collaborate with architects RTL designers and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

As a Physical Design intern you will be responsible for realizing our front-end designs in silicon helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks automate final design checks and advise RTL design decisions.

You may be a good fit if you have:

• Progress towards a Bachelors Masters or PhD degree in electrical engineering computer engineering or a related field.

• Familiarity with high-speed digital logic

• Exposure to ASIC or SoC design concepts

• Familiarity with SystemVerilog UVM or Python

• Familiarity with verification work and writing test benches

• Familiarity with physical design flows and tooling

• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with:

• Familiarity with transformer models and machine learning

• Familiarity with numerical representations and functions (RTL)

• Familiarity with clocking and reset schemes (RTL/PD)

• UVM or formal verification experience (DV)

• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details:

• 12-week paid internship (June - August 2026)

• Generous housing support for those relocating

• Daily lunch and dinner in our office

• Based at our office in San Jose CA

• Direct mentorship from industry leaders and world-class engineers

• Opportunity to work on one of the most important problems of our time

For any questions contact .

How were different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures which creates a market for single-model ASICs.

We are a fully in-person team in West San Jose and greatly value engineering skills. We do not have boundaries between engineering and research and we expect all of our technical staff to contribute to both as needed.

Required Experience:

Intern