Senior Staff Engineer, Serdes Layout Design

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Our technology solutions power the tools you use every day--including smartphones electric vehicles hyperscale data centers IoT devices and so much more. Here youll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of whats possible and powering the future.

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Samsung Semiconductor Inc. (SSI) is advancing the worlds technology. As a leader in Memory System LSI and LCD technologies our US teams contribute to breakthroughs in 5G SOC memory and display. With our global perspective and diversity of thought we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Location: Daily onsite presence at our San Jose CA headquarters in alignment with our Flexible Work policy

What Youll Do

As a senior high speed mixed-signal layout/analog layout engineer you will be working with circuit designers located in San Jose California USA to accomplish layout tasks. Circuits that you will need to work on includes High Speed RX (receiver) TX (transmitters) PLL CDR Analog reference circuits and so on. You should have experiences doing layout with sub-micron CMOS technologies

Youll work with designers to optimize the performance and power consumption of SERDES analog PHY.

Location: Daily onsite presence at our San Jose CA headquarters in alignment with our Flexible Work policy

• Working with remote circuit designers to determine the chip floorplan. You need to come up with strategies to optimize the parasites reduce area and improve High Speed SERDES/analog performance.
• You need to be able to estimate schedule and come up with plan how to get things done within a dedicated time frame.
• You should be able to read the design document provided by the foundry and figure out how to resolve issues like latch-up and DRC.
• Perform custom layout using Virtuoso and be able to get LVS/DRC clean.
• You should be familiar with CAD tools including Virtuoso Calibre LVS DRC SkillCad and so on.
• Desired to have experience on chip level design like bump pad and ESD strategies.
• Good communication skills to discuss with circuit designer.

What You Bring

• Bachelors with 15 years Masters with 13 years or PhDs with 10 years of experience.
• Experience in RF/analog/mixed-signal/serdes layout design of deep submicron CMOS circuits and recent experience on advance nodes including FinFET and GAA technologies
• High level of proficiency in interpretation of CALIBRE DRC ERC LVS reports
• Familiar with analog/mixed-signal related circuit layout including high-speed I/O block such as comparator/transmitter/receiver/PLLs and so on.
• Experience with CADENCE or MENTOR GRAPHICS layout tools
• Good communication skills with design leads as well as engineers for schedule planning
• Experience of leading a complicated layout project and tape-out successfully.
• Programming knowledge in SKILL Perl and/or Python is a bonus
• Youre inclusive adapting your style to the situation and diverse global norms of our people.
• An avid learner you approach challenges with curiosity and resilience seeking data to help build understanding.
• Youre collaborative building relationships humbly offering support and openly welcoming approaches.
• Innovative and creative you proactively explore new ideas and adapt quickly to change.

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