Sr. Manager, ASIC Design
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Job Location:
San Jose, CA - USA
Yearly Salary:
$ 210000 - 240000
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
Credo is engineering the future of high-speed connectivity for the AI-driven world.With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges we deliver industry-leading solutions that power the next generation of cloud AI and hyperscale data centers.
Credo is pioneering a systems-level approach to connectivity integrating hardware software and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment improving performance and reducing complexity across their infrastructure.
At Credo youll be part of a team of world-class technologists and engineers that thrive on pushing the limits of whats possible for some of the worlds most important companies. Our portfolio includes cutting edge solutions including our softwareoptical DSPs PCIe/CXL products SerDes IP and advanced Active Electrical Cables(AECs) all designed for maximum performance energy efficiency and scalability.
We foster a culture oftechnical excellence collaboration and continuous learning where your ideas can shape the future of connectivity. From silicon architects to systems engineers every role at Credo contributes to solving real-world problems at scale.
Join us and help us architect the next generation of disruptive networking technologies because at Credo We Connect.
AbouttheRole
-outsandpartnerwithsystemteamsforchipbring-upandvalidation.
Responsibilities
- Leadateamofengineerstodeliverchipsfromspecificationthroughtapeout.
- Mentorjuniorengineersondesignmethodologiesverificationflowsandbestpractices.
- Developandmaintaindetailedmicroarchitectureanddesignspecifications.
- Designimplementanddebugcomplexlogicblocks.
- IntegrateandvalidateIPsfrominternalandexternalvendors.
- Supportfront-endintegrationactivitiesincludingLintCDCsynthesisandECOprocesses.
- Createfunctionaltestsandtestbenches;performRTLandgate-levelverificationandsimulations.
- CollaboratewithverificationDFTandphysicaldesignteamstoensuresuccessfultapeout.
- Bringupvalidateanddebugfunctionalfeaturesonsilicon.
- Workcloselywithsoftwarefirmwareapplicationsandsystemsteamstodeliverahigh-qualityproduct.
BasicQualifications
- MSdegreeinEE/CSwith10yearsofrelevantexperience.
- Deepunderstandingofdigitallogicdesignandcomplexsynchronous/asynchronousinterfaces.
- ProficientinVerilog/SystemVerilogRTLdesign.
- Knowledgeofsynthesisandstatictiminganalysis.
- Experiencedevelopingtestbenchesandtestcases;familiaritywithUVM.
- Experiencewithgate-levelsimulationschipbring-upandvalidation.
- Proventrackrecordofsuccessfulproductiontape-outs.
- Hands-onexperiencewithSTAandtimingclosure.
- FamiliaritywithDFTmethodologyandphysicaldesignflow.
PreferredQualifications
- Expertiseinscriptinglanguages(PythonTclPerlShell).
- Strongplanningandestimationskills.
- Excellentcommunicationandleadershipabilities.
The base salary range for this position is $200000 $230000 a year. The base salary ultimately offered is determined through a review of education experience training skills qualifications and location. This position is also eligible for a discretionary bonus equity and a full range of medical and other benefits.
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Required Experience:
Senior Manager
Key Skills
- Haskell
- Construction Experience
- Management Experience
- Autodesk
- Design Thinking
- Library Services
- Drafting
- Project Management
- Relationship Management
- Adobe Photoshop
- Autocad
- Child Protective Services
