Staff Senior Staff DFT Engineer
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Job Location:
Monthly Salary:
Posted on:
20 hours ago
Vacancies:
1 Vacancy
Job Summary
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs from architecture and design all the way through layout packaging prototype validation and production ramp up. This group provides technology development EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses.What You Can Expect
Own and define DFT strategy and methodology for complex Subsystem in ASIC/SoC programs ensuring scalability robustness and alignment with Marvells product roadmap.
Architect advanced DFT solutions (scan MBIST OCC boundary scan hierarchical flows SSN/IJTAG).
Lead crossfunctional collaboration with RTL synthesis physical design verification and product engineering teams to ensure seamless integration of DFT features.
Establish best practices and standards for DFT implementation SpyGlass DFT rule compliance and testability signoff across projects.
Drive automation initiatives by developing and deploying scripting solutions (TCL Python Perl Shell) to improve efficiency coverage and repeatability of flows.
Mentor and guide junior and midlevel engineers fostering technical growth and ensuring consistent methodology execution across the organization.
Influence design architecture decisions by providing early DFT input to maximize test coverage and minimize silicon risk.
Lead presilicon validation and postsilicon bringup efforts ensuring firsttimeright silicon and smooth transition to production test.
Partner with product/test engineering to optimize yield reduce test cost and improve overall quality metrics.
Represent Marvell in technical forums (internal and external) by contributing to DFT innovation tool evaluations and industry standards.
What Were Looking For
Bachelors/ Masters degree in Electrical/Electronics Engineering VLSI or related field with 5 to 12 years of experience in DFT for complex ASIC/SoC designs.
Strong fundamentals in Digital Circuit Design and Logic Design.
Proven expertise in:
Scan insertion and ATPG tools (Synopsys Cadence Mentor).
MBIST/OCC validation flows.
Hierarchical DFT and SDC constraint management.
SSN design and IEEE 1687 IJTAG standards for embedded instrumentation.
SpyGlass DFT rules for design quality and testability compliance.
Solid understanding of RTL design synthesis STA and physical design flows.
Handson scripting experience (TCL Python Perl Shell etc.) for automation and flow development.
Handson experience with silicon bringup debug and production test optimization.
Experience mentoring junior engineers and driving technical growth within teams.
Demonstrated ability to lead crossfunctional teams influence design architecture and establish DFT best practices.
Excellent problemsolving communication and collaboration skills.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.
#LI-RS1Required Experience:
Staff IC
Key Skills
- Computer Science
- Docker
- Kubernetes
- Python
- VMware
- C/C++
- Go
- System Architecture
- gRPC
- OS Kernels
- Perl
- Distributed Systems
About Company
Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
