Senior Physical Design Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

This role is based in the Marvell office in Burlington VT. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Relocation will be required. Remote work from a different site is not offered at this time.

Key responsibilities include:

• Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner.

• Implement/support designs with multi-voltage designs through all aspects of implementation (place and route static timing physical verification) using industry standard EDA tools.

• Work with RTL design teams to drive assembly and design closure.

• Provide technical direction coaching and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.

• Write scripts in Shell Python and TCL to extract data and achieve productivity enhancements through automation.

What Were Looking For

• Bachelors degree in Computer Science Electrical Engineering or related fields and at least 1-3 years of related professional experience or Masters degree in Computer Science Electrical Engineering or related fields or equivalent professional experience in lieu of a formal degree
• Expertise in full-chip & sub-hierarchy integration
• Experience integrating and taping out large designs utilizing a digital design environment
• Good understanding of RTL to GDS flows and methodology
• Good scripting skills in TCL/Python
• Knowledge of Verilog
• Experience with Cadence Innovus is preferred

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.