Senior Digital Design Engineer

Credo is engineering the future of high-speed connectivity for the AI-driven world.With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges we deliver industry-leading solutions that power the next generation of cloud AI and hyperscale data centers.

Credo is pioneering a systems-level approach to connectivity integrating hardware software and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment improving performance and reducing complexity across their infrastructure.

At Credo youll be part of a team of world-class technologists and engineers that thrive on pushing the limits of whats possible for some of the worlds most important companies. Our portfolio includes cutting edge solutions including our softwareoptical DSPs PCIe/CXL products SerDes IP and advanced Active Electrical Cables(AECs) all designed for maximum performance energy efficiency and scalability.

We foster a culture oftechnical excellence collaboration and continuous learning where your ideas can shape the future of connectivity. From silicon architects to systems engineers every role at Credo contributes to solving real-world problems at scale.

Join us and help us architect the next generation of disruptive networking technologies because at Credo We Connect.

About the Role

Were looking for a Senior Digital Design Engineer to lead front-end ASIC design efforts including architecture implementation and verification of complex logic blocks. Youll collaborate across design verification and physical teams to ensure successful tape-outs while contributing to microarchitecture specs IP integration and chip bring-up. This role combines technical depth with cross-functional teamwork to deliver high-performance digital solutions.

Responsibilities

• Write microarchitecture and/or design specifications.
• Architect/design implement and debug complex logic blocks.
• Understand and integrate complex IPs from internal and external IP vendors.
• Support all front-end integration activities like Lint CDC Synthesis and ECO.
• Develop functional tests/testbenches and run functional RTL and Gate-Level verification/simulations.
• Work with other ASIC Design/Verification DFT and Physical Design Engineers in achieving a successful tape out.
• Collaborate with Software Firmware Applications and Systems teams to ensure a high-quality product.
• Bring-up validate and debug functional features in the chip.

Basic Qualifications

• BS or MS in Electrical Engineering Computer Engineering or related field with 510 years of experience in digital ASIC design
• Strong understanding of digital logic design including synchronous and asynchronous interfaces
• Proficiency in Verilog/SystemVerilog RTL design
• Experience developing testbenches and test cases for block-level and top-level verification
• Familiarity with UVM methodology
• Hands-on experience with gate-level simulations chip bring-up and validation
• Knowledge of synthesis and static timing analysis
• Proficiency in scripting languages such as Python Tcl Perl or Shell
• Strong planning and estimation skills
• Effective communicator and collaborative team player

The base salary range for this position is $140000 $170000 a year. The base salary ultimately offered is determined through a review of education experience training skills qualifications and location. This position is also eligible for a discretionary bonus equity and a full range of medical and other benefits.

Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race color religion gender sex sexual orientation national origin genetic information age disability veteran status or any other legally protected basis.

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Required Experience:

Senior IC