Digital Layout Design Specialist

Beaverton, OR - USA

Monthly Salary: Not Disclosed

Posted on: 30+ days ago

Vacancies: 1 Vacancy

Job Summary

Imagine yourself at the center of our SOC design effort collaborating with all fields playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group you will be responsible to deliver PDV clean layout including the following: -Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies. -Reviewing and analyzing floorplans and complex circuits with circuit designers. -Running a complete set of layout design verification tools available on megacells completed. -Working with the circuit design team to plan schedule work and negotiate layout tradeoffs as needed. -Interpretation of LVS DRC and ERC report to find the fastest way to complete layouts. -Exceed engineering specifications and expectations. -Use advanced CAD tools mask design knowledge to layout corrections and robust physical design representation of circuits.

5 years experience in building complex custom layout

Associates Degree or Bachelors Degree in Engineering preferred
Deep knowledge of tools used to build and verify custom layout
We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits used in high performance microprocessors.
Experience designing low noise low power datapaths SRAM Register files layout structures etc.
High level proficiency in layout floorplanning standard cell planning and hierarchical layout assembly.
Good understanding of issues with RC delay electromigration self heating and cross capacitance.
Recognize failure prone circuit and layout structures dedicatedly work with designers for the best approach to problems.
Great skills on interpretation of CALIBRE DRC ERC LVS etc. reports.
Knowledge of MENTOR GRAPHICS or CADENCE layout tools
Scripting skills in CSH PERL or SKILL are considered a plus but not required.
Experience in layout automation is considered a plus but not required.
Experience in memory compiler development is considered a plus but not required.
Excellent communication skills and able to work with multi-functional teams.

Required Experience:

5 years experience in building complex custom layout

Associates Degree or Bachelors Degree in Engineering preferred
Deep knowledge of tools used to build and verify custom layout
We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits used in high performance microprocessors.
Experience designing low noise low power datapaths SRAM Register files layout structures etc.
High level proficiency in layout floorplanning standard cell planning and hierarchical layout assembly.
Good understanding of issues with RC delay electromigration self heating and cross capacitance.
Recognize failure prone circuit and layout structures dedicatedly work with designers for the best approach to problems.
Great skills on interpretation of CALIBRE DRC ERC LVS etc. reports.
Knowledge of MENTOR GRAPHICS or CADENCE layout tools
Scripting skills in CSH PERL or SKILL are considered a plus but not required.
Experience in layout automation is considered a plus but not required.
Experience in memory compiler development is considered a plus but not required.
Excellent communication skills and able to work with multi-functional teams.

Required Experience:

Key Skills

Acting
Electrical Controls
Actuarial
Attorney
Drafting
Adobe Photoshop

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